CPL CPU Architect & RTL Design Engineer

AMD; Dublin; Hybrid; EUR 120,000 - 150,000; Full time

Benefits offered by this job

AMD benefits at a glance

Hybrid work (0-3 days from home)

Job summary

AMD in Dublin, Ireland, is seeking a CPL CPU Architect/RTL Design Engineer to drive the definition, RTL design, and integration of Clocking, Reset and Power in AMD's next-generation CPUs. You will work with a skilled team to deliver from concept to tape-out, shaping the architecture of CPL IP and related caches.

You will collaborate across logic, physical, and verification teams to meet stringent performance and power targets, contributing to AMD's ambitious CPU roadmap in a hybrid work

Qualifications

• Bachelors or Masters in computer engineering or Electrical Engineering.
• Proficiency with Verilog HDL and clock/power domain crossing concepts.
• Experience with power management concepts.
• Understanding of modern CPU architecture and cache/IP design is a plus.
• Ability to collaborate across design, physical design and verification teams.

Responsibilities

• Define and implement CPL microarchitecture for AMD CPUs.
• Deliver a design from concept through tapeout under challenging requirements.
• Gain experience with Static Timing, CDC/Gate CDC, and Static Power analysis.
• Identify customer challenges and address them with AMD value propositions.
• Contribute to high performance, high frequency, and power-efficient caches and interfaces.

Skills

Verilog HDL

Clock/Power Domain Crossing

Power Management concepts

Education

Bachelors or Masters in computer engineering / Electrical Engineering

Job description

AMD in Dublin, Ireland, is seeking a CPL CPU Architect/RTL Design Engineer to drive the definition, RTL design, and integration of Clocking, Reset and Power in AMD's next-generation CPUs. You will work with a skilled team to deliver from concept to tape-out, shaping the architecture of CPL IP and related caches.

You will collaborate across logic, physical, and verification teams to meet stringent performance and power targets, contributing to AMD's ambitious CPU roadmap in a hybrid work