Analog / Mixed-Signal SerDes Design Engineer - Cork, Ireland

Qualcomm; Cork; On-site; EUR 60,000 - 80,000; Full time

Job summary

A multinational technology company in Cork is seeking an Analog / Mixed-Signal design engineer to develop high-speed PHY receivers and drivers. Ideal candidates will have a Master's/Ph.D. in engineering and at least 3 years of relevant experience, with a focus on low-power circuit design and the ability to work within a dynamic team. Responsibilities include designing custom IP and ensuring adherence to advanced layout practices.

Qualifications

• 2+ years ASIC design, verification, or related work experience.
• Minimum 3 years experience in high-speed applications.
• Experience in designing complex analog circuits.

Responsibilities

• Design analog/mixed-signal hard macros for SerDes IP Design team.
• Create design specifications and behavioral models.
• Conduct quality assurance procedures on developed hard macros.

Skills

Transistor-level analog mixed-signal design experience

SPICE simulators and schematic capture tools

Designing op-amps, bandgaps, differential amplifiers

Understanding of signal integrity in high-speed design

Full-custom analog layout techniques

Excellent communication skills

Education

Master’s or Ph.D. degree in Science, Engineering, or related field

Bachelor’s degree in Science, Engineering, or related field

Tools

SPICE

Verilog

Job description

Company:

QT Technologies Ireland Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

About the role

Qualcomm’s SerDes PHY team is seeking Analog / Mixed‑Signal design engineers to join our growing team in Cork, Ireland. The successful candidate will work on analog and mixed‑signal integrated circuits for high speed PHY receivers and drivers, VCOs, PLLs, and a range of other custom IP for Qualcomm Mobile, Auto, IoT & Compute SoC products. The primary focus of the work is on low‑power and low‑voltage mixed‑signal design with emphasis on advanced nanometer FinFET and GAA technology nodes.

The successful candidate will both design key circuit blocks and work closely with layout engineers to ensure the layout is fully optimised and complies with best analog layout practices. You will be directly involved in delivering next‑generation SerDes and PLL designs for Qualcomm SoCs and will be part of a large analog mixed‑signal design team involved in architecture analysis and IP delivery in leading‑edge FinFET and GAA process technology nodes at 3nm and below.

The role requires industry experience in transistor‑level circuit implementations or highly relevant academic experience in a Masters’ or PhD program focused on full custom analog circuit design using nanometer CMOS technologies. In addition to Analog and Mixed‑Signal circuit design expertise, good understanding of device physics, analog circuit custom layout, power distribution networks (PDN), mixed‑signal design flow, SoC top‑level integration and IC Design Tools are desired.

Responsibilities:

• Architecture, design, and development of analog / mixed‑signal hard macros for the SerDes IP Design team
• Perform custom circuit design in the latest FinFET CMOS process technologies and beyond to support the delivery of SerDes IP
• Participate in internal customer requirements discussions
• Create design specifications
• Create behavioural models in Verilog
• Set‑up, run and analyse circuit simulations
• Perform quality assurance procedures on developed hard macros
• Deliver hard macros and support customer integration and testing
• Perform silicon characterization analysis and prepare silicon verification reports

Skills and Experience we would love to see:

• Master’s or Ph.D. degree in Science, Engineering, or related field
• A minimum of 3‑years of transistor‑level analog mixed‑signal design experience, preferably in high‑speed wireline SerDes, PLL, DDR or other high‑speed applications
• Experience in SPICE simulators and schematic capture tools
• Experience in designing op‑amps, bandgaps, differential amplifiers, VCO, PLL, DLL
• Experience in high‑speed SerDes block‑level designs such as transmitters, receivers, high‑speed VGA, CTLE, CDR, etc.
• Understanding of signal integrity in high‑speed wireline design is preferred
• Scripting to automate circuit design and verification work
• Full‑custom analog layout techniques and the ability to complete layout extraction verification and sign‑off
• Excellent communication skills and ability to contribute strongly within a high‑performance team

Minimum Qualifications:

• Bachelor’s degree in Science, Engineering, or related field
• 2+ years ASIC design, verification, or related work experience

Qualcomm is an equal‑opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. Please contact disability‑[e-mail].