Senior Architect (GPU/NPU Frontier Technology & System Innovation)

Hong Kong Alioth Tech Solution Limited; Hong Kong; Sur place; HKD 1 200 000 - 1 700 000; Plein temps

Résumé du poste

Hong Kong Alioth Tech Solution Limited is seeking a Senior Architect (GPU/NPU frontier technology and system innovation) to drive hardware architecture innovation for large-model inference. The role emphasizes understanding models, compilers, and runtimes to influence chip, memory, interconnects, and full-system design.

Ideal candidates will have deep expertise in NPU chips, high-speed interconnects, or complete systems, with a cross-domain perspective and a focus on performance, energy

Qualifications

• Experience in hardware architecture for AI accelerators.
• Ability to analyze performance bottlenecks and optimize energy use.
• Cross-domain thinking across hardware and software domains.

Responsabilités

• Hardware architecture exploration for large-model inference, including memory hierarchy and interconnects.
• Analyze compute and memory-access patterns and optimize resource allocation and interfaces with software stacks.
• Lead research in key hardware technologies and contribute to solution design across chips and systems.

Connaissances

Hardware architecture

Performance analysis

Energy efficiency

Outils

Compiler scheduling

Runtime optimization

Hardware-software co-design

Description du poste

Senior Architect (GPU/NPU Frontier Technology & System Innovation)

We are developing next-generation NPUs and computing systems with large-model inference as a primary application, and are looking for a senior architect with technical depth and a systems perspective to drive hardware architecture innovation, frontier technology exploration, and validation of key technical solutions.

This role is centered on hardware architecture and requires combined hardware/software knowledge and analytical capability — understanding the execution characteristics of large models, compilers, and runtimes, and translating them into design and optimization decisions across chips, memory, interconnect, and complete systems. Strong emphasis is also placed on performance, energy efficiency, cost efficiency, and engineering feasibility under domestic process and supply-chain conditions.

We welcome technical experts with deep expertise in at least one of the following areas — NPU chips, high-speed interconnect, or complete systems — and with a cross-domain perspective.

Key Responsibilities

• Hardware architecture exploration for large-model inference. Research NPU compute architecture, memory hierarchy, data movement, and interconnect mechanisms around the requirements of large-model inference, and propose innovative ideas, architecture improvements, and alternative solutions with product value.
• Workload analysis and hardware-software co-design. Analyze the compute, memory-access, and communication characteristics of representative models in stages such as Prefill and Decode; combined with operator mapping, compiler scheduling, runtime, and communication libraries, identify hardware bottlenecks and optimize resource allocation and hardware-software interfaces.
• Focused research on key hardware technologies. Based on individual expertise, lead research and solution design in one or more of the following directions