Senior Processor Architect

NIF; Greater London; Hybrid; GBP 120,000 - 180,000; Full time

Job summary

Fractile is seeking a Processor Architect to define and drive the architecture of core compute engines, ISA definitions and on-chip interconnects. You’ll work with design, verification and physical teams to translate intent into silicon, with hands-on performance modelling and rigorous documentation.

You will own architecture specs, specify memory hierarchies and execution units, and mentor colleagues while engaging with customers and leadership.

Qualifications

• Proven experience as a Processor Architect or similar, in HPC or semiconductors.
• Deep knowledge of compute engines, memory hierarchies and RTL flows.
• Experience from exploration to tapeout and post-silicon validation.
• Ability to define performance and power budgets across designs.

Responsibilities

• Define and own compute engine architecture specifications with trade-offs.
• Lead architectural exploration from concept to specification across teams.
• Specify execution units, memory hierarchy and instruction flows.
• Develop performance models and simulators to guide decisions.
• Collaborate with system, software and modelling teams for real-world performance.
• Evaluate new techniques to inform the architectural roadmap.
• Mentor team members and raise rigor in documentation.
• Represent architecture in reviews, discussions and customer engagements.

Skills

Processor Architecture

RTL design

Performance modelling

Cross-functional collaboration

Power and area budgeting

Communication skills

Tools

gem5

SystemC

Job description

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

As Processor Architect, you'll define and drive the architecture of our core compute engines, ISA definitions and programming models through to memory hierarchies, and on-chip interconnects. This isn't just about hitting PPA targets on a spreadsheet; you'll work closely with logical design, physical design, and verification teams to translate architectural intent into working silicon that performs in the real world. Expect to be hands-on in performance modelling, detailed specification writing, bottleneck analysis, pre and post-silicon validation. You'll be the driving force behind the computational heart of our products ensuring every cycle counts and every watt is well spent.

Key Responsibilities

• Define and own the compute engine architecture specifications, balancing performance, flexibility, power, area, and design complexity.
• Lead architectural exploration from early concept through to specification, coordinating with modelling, implementation, verification, and physical design teams.
• Specify execution units, memory hierarchy, instruction sets and flow — making principled trade-offs at every level.
• Help build and maintain performance models and simulators to guide architectural decisions with data.
• Partner with the system architecture and software/modelling teams to ensure the processor delivers real-world application performance, not just benchmark wins.
• Evaluate emerging techniques — compact number formats, novel compute paradigms, advanced packaging options — to inform the architectural roadmap.
• Act as a technical mentor, raising the bar for rigour in performance analysis and architectural documentation across the team.
• Represent compute engine architecture in technical reviews, partner discussions, and customer engagements.

Skills & Experience

• Proven experience as a Processor Architect, CPU/GPU Architect, or similar role in semiconductor or high-performance computing domains.
• Deep understanding of compute engine and processor architecture and design, including matrix and vector centric floating-point arithmetic and memory hierarchies.
• Strong grasp of RTL design flows and physical design constraints and how they feed back into architectural choices.
• Experience taking processor designs from early exploration through to tapeout and post-silicon performance characterisation.
• Demonstrated ability to define and manage performance and power budgets and navigate complex trade-offs.
• Comfortable working across many disciplines, including architecture, modelling, implementation, verification, and software.
• Excellent communicator who can bridge architectural depth with system-level and product-level context.

Desirable

• Background in AI acceleration, vector/matrix compute, or domain‑specific processor design.
• Experience with architectural performance modelling tools and frameworks (gem5, SystemC, custom cycle‑accurate simulators).
• Familiarity with compiler and toolchain interactions, understanding how software maps to hardware.
• Prior start‑up or scale‑up experience, someone who thrives in ambiguity and fast iteration.

How we work

• Ownership and execution: you will have full agency to drive your work forward
• Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
• Full‑stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
• Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
• Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter whose it is

About us

• Founded in 2022, a team of 80+, which is expanding rapidly
• Modern, open offices in London and Bristol
• Collaborative, problem‑solving culture built on deep curiosity, entrepreneurial initiative and technical fluency

Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.