Senior/Principal Physical Design Engineer

Fractile; City Of London; On-site; GBP 70,000 - 90,000; Full time

Job summary

A cutting-edge technology company in London is seeking an experienced physical design engineer to drive ASIC/SoC implementations. The role requires expertise in advanced technology nodes, EDA tools, and a solid understanding of CMOS technology. Ideal candidates will have over 7 years of experience and a strong collaborative spirit. This is an opportunity to be part of a pioneering team shaping the future of AI innovation.

Qualifications

• 7+ years of experience in physical design for advanced technology nodes.
• Solid understanding of CMOS technology and semiconductor physics.
• Experience with low-power design methodologies and power optimisation techniques.

Responsibilities

• Drive the physical implementation of ASIC/SoC designs.
• Work on synthesis, timing analysis, and optimisation for best PPA metrics.
• Collaborate with DFT engineers for design-for-test integration.

Skills

EDA tools proficiency

Physical design expertise

Problem-solving skills

Team collaboration

Scripting languages (TCL, Perl, Python)

Education

Bachelor’s, Master’s or PhD in Electrical Engineering

Tools

Cadence Innovus

Synopsys ICC2

Mentor Graphics Calibre

Job description

Overview

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

Responsibilities

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.

Qualifications

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.