Senior FPGA Engineer (DV Equities)

DV Trading LLC; Greater London; On-site; GBP 70,000 - 90,000; Full time

Job summary

DV Trading LLC is seeking a Senior FPGA Engineer to join their semi-systematic equities team in Greater London. The successful candidate will architect and deliver ultra-low-latency FPGA trading systems that drive the firm's competitive edge in global equity and futures exchanges. This role involves leading a team, designing high-throughput FPGA firmware, and optimizing hardware for performance. Applicants should have over 5 years of FPGA design experience and expertise in SystemVerilog. The company offers an inclusive work environment.

Qualifications

• 5+ years of hands-on FPGA design and development experience in high-frequency systems.
• Expert-level proficiency in SystemVerilog targeting Xilinx platforms.
• Understanding of networking and low-level protocols (10G Ethernet, multicast).

Responsibilities

• Lead and mentor a team of FPGA engineers in hardware solutions.
• Design and implement high-throughput FPGA firmware for trading.
• Build scalable FPGA architectures supporting major exchanges.

Skills

FPGA design and development

SystemVerilog

Networking protocols

Low-latency hardware design

Job description

About Us

Founded 20 years ago and headquartered in Chicago, the DV Group of financial services firms has grown to more than 600 people operating throughout North America, Europe and Asia. Since spinning out of a large brokerage firm in 2016, DV Trading has rapidly scaled as an independent proprietary trading firm utilizing its own capital, trading strategies, and risk management methodologies to provide liquidity to worldwide financial markets and hedging opportunities to commodity producers and users. Now, DV group affiliates include two broker dealers, a cryptocurrency market making firm, and a bourgeoning investment adviser.

Role Overview

We are looking for an exceptional Senior FPGA Engineer to join our semi-systematic equities team. In this role, you will architect and deliver ultra-low-latency FPGA trading systems that drive our competitive edge across global equity and futures exchanges. This position offers the opportunity to lead, innovate, and push the limits of hardware performance in a fast-paced trading environment.

Key Responsibilities

Technical Leadership

• Lead and mentor a team of FPGA engineers developing next-generation hardware solutions for market making.
• Architect and implement ultra-low-latency trading systems optimized for global equity and futures markets.
• Define and execute the technical vision and roadmap for FPGA-based trading infrastructure.
• Partner closely with quantitative researchers, software developers, and network engineers to deliver integrated, high-performance trading platforms.

System Development

• Design and implement high-throughput FPGA firmware for market data feed handling and order execution.
• Build modular, reusable, and scalable FPGA architectures supporting exchanges such as NYSE, NASDAQ and CBOE.
• Develop robust testing frameworks and automated deployment pipelines to ensure stability and reliability in production.

Required Qualifications

• 5+ years of hands-on FPGA design and development experience, ideally within high-frequency or market‑making systems.
• Expert‑level proficiency in SystemVerilog targeting Xilinx platforms.
• Deep understanding of networking and low‑level protocols (10G Ethernet, multicast, MAC/PCS layers).
• Proven track record in ultra‑low‑latency hardware design and performance optimization.

DV is not accepting unsolicited resumes from search firms. Only search firms with valid, written agreements with DV should submit resumes in response to DV's posted positions. All resumes submitted by search firms to DV via e-mail, the Internet, personal delivery, facsimile, or any other method without a valid written agreement shall be deemed the sole property of DV, and no fee will be paid in the event the candidate is hired by DV. DV is proud to be an equal opportunity employer and committed to creating an inclusive environment for all employees.