Senior Design Engineer

Jobtailor; Southampton; On-site; GBP 60,000 - 85,000; Full time

Job summary

Jobtailor in the United Kingdom is seeking an experienced RTL engineer to translate requirements into micro-architectures for FPGA/ASIC implementations. You will deploy designs on FPGA platforms for validation and integrate with the broader design flow.

The role requires expert SystemVerilog/Verilog proficiency, timing optimization, and collaboration across teams. You will document designs, create testbenches, and use modern EDA tools to deliver high-throughput data processing solutions.

Qualifications

• Expert knowledge of RTL languages (Verilog/SystemVerilog) for complex ASIC/FPGA products.
• Strong track record delivering digital designs for ASIC/FPGA industries.
• Experience optimizing timing and hardware resources for high throughput data processing.
• Experience collaborating across teams to deliver integrated solutions.
• Experience with technical documentation: design specs, user guides, verification plans.
• Expert user of EDA tools for simulation and synthesis.
• Knowledge of communications signal processing algorithms (error correction, equalisation, channel estimation, beamforming).
• Familiarity with AMBA bus protocols and UVM verification for IP.
• Experience with C++/SystemC for design modelling and integration.
• Experience with high-speed interfaces like PCIe or JESD.
• Knowledge of Python scripting.
• Understanding of project methodologies (agile/waterfall, requirements traceability).
• Experience with AMD FPGAs or other EDA ASIC backends tools.

Responsibilities

• Work with Algorithm and System Architecture teams to translate requirements into RTL micro-architectures.
• Implement designs targeting FPGA and ASIC with testbenches.
• Deploy designs onto FPGA development platforms for validation and integration.
• Engage with engineering methodologies to improve design flow and product quality.
• Collaborate across the full design flow: micro-architecture, design, verification, physical implementation and optimization.

Skills

Verilog/SystemVerilog RTL

ASIC/FPGA design

UVM verification

C++/SystemC modelling

Python scripting

PCIe/JESD interfaces

AMBA protocols

Synthesis & timing analysis

EDA tools

Power management techniques

Testbench development

Job description

Responsibilities

• Work closely with the Algorithm and System Architecture teams to understand requirements and translate them into micro-architectures for RTL implementations
• Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches
• Deploy your designs onto the latest FPGA development platforms for validation and system integration
• Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product
• Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA

Requirements

• Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
• A strong skillset in delivering digital designs in the ASIC and FPGA industry
• Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
• Track record in collaborating across teams to produce integrated solutions
• Experience in technical documentation writing – design specifications, user guides, verification plans
• Expert user of EDA tools for simulation and synthesis
• Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
• Familiarity with the AMBA bus protocols
• Understanding of UVM verification techniques or practical experience using UVM for IP verification
• Experience using C++/SystemC for design modelling and integration
• Experience with high speed interfaces such as PCI-E or JESD
• Knowledge of a scripting language, such as Python
• Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
• Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools

Core Competencies

Demonstrates expert knowledge in RTL languages such as Verilog and SystemVerilog for ASIC and FPGA designs, with a strong focus on optimization techniques for high throughput data processing. Proficient in collaborating across teams to deliver integrated solutions while adhering to established engineering methodologies.