Research Associate- Heterogeneous Integration: Manufacturing Pathways,Test&Supply Chain
The University of Sheffield
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Benefits offered by this job
Job summary
The University of Sheffield invites applications for a Research and Innovation Fellow in Manufacturing Pathways, Test and Supply Chain within the CHIMES² CTO Office. You will lead landscape analysis, roadmapping, and knowledge infrastructure across back-end physical implementation and supply chains.
Candidates will develop an independent research theme, co-author papers, and engage with UK and international partners to shape national semiconductor strategy.
Qualifications
- Demonstrated credibility in physical implementation for HI systems.
- Experience with advanced packaging and back-end design flows.
- Ability to synthesize landscape analyses into roadmaps and policy briefs.
Responsibilities
- Lead landscape analyses mapping needs for HI devices and interposers.
- Develop roadmaps for physical implementation and manufacturing transitions.
- Represent CHIMES² at global forums and contribute to Design Commons outputs.
Skills
Education
Tools
Job description
The University of Sheffield is a remarkable place to work. Our people are at the heart of everything we do. Their diverse backgrounds, abilities and beliefs make Sheffield a world-class university.
We offer a fantastic range of benefits including a highly competitive annual leave entitlement (with the ability to purchase more), a generous pensions scheme, flexible working opportunities, a commitment to your development and wellbeing, a wide range of retail discounts, and much more. Find out more about our benefits (opens in a new window) and join us to become part of something special.
CHIMES² — the Centre for Heterogeneous Integrated MicroElectronic and Semiconductor Systems — is one of the UK’s national semiconductor research-translation programmes, a £16.3M Innovation and Knowledge Centre led by the University of Sheffield. We are appointing a Research and Innovation Fellow in Manufacturing Pathways, Test and Supply Chain to its CTO Office. This is not a conventional postdoctoral research post. Its core is landscape analysis and roadmap intelligence — reading the international state of the art in packaging, test and supply chain, identifying the gaps the UK must close, and turning that into the knowledge infrastructure a national programme runs on. A research theme of your own is developed alongside that work, not instead of it.
This post focuses on the ‘physical’ layer of heterogeneous integration — the realisation of system architecture into physical package configurations, assembly processes and manufacturable implementations. This spans back-end physical implementation (place-and-route, physical verification, DRC/LVS across heterogeneous stacks, timing closure under packaging parasitics), advanced packaging architecture selection (2.5D, 3D, hybrid bonding, fan-out), manufacturing pathway management, known-good-die test strategy, and the UK and global supply chain for heterogeneous integration.
We are advertising two paired CTO Office posts in parallel: this post in Manufacturing Pathways, Test and Supply Chain (the physical layer) and a companion post in Systems Architecture and Design (the logical layer). The logical-to-physical handoff — where system partitioning decisions are handed from architectural intent to physical realisation — is the primary interface between the two posts, and both post holders are expected to develop working familiarity with each other’s domain. Candidates whose interests span both layers are welcome to apply for both; please indicate this in your cover letter.
You will join the Microelectronics and Integrated Semiconductor Systems Team within the Quantum and Semiconductor Systems (QSS) Group — one of the UK’s largest and most successful semiconductor research environments. The Team hosts Sheffield’s leadership role for CHIMES², which brings together partner universities including Cambridge, Oxford, Edinburgh, Manchester, Newcastle, Strathclyde, Queen’s University Belfast and King’s College London, alongside the Science and Technology Facilities Council. Industrial partners include, among others, Imec, Arm, Pragmatic, Cadence, Synopsys and Siemens EDA. The CTO Office sits at the centre of the programme’s technical intelligence function; you will collaborate closely with the newly established CHIMES² engineering cohort, though the CTO Office and the engineering team are distinct functions.
- It is a national-programme intelligence role. You will lead landscape and roadmap work that directly shapes CHIMES² research priorities, demonstrator projects, and the Design Commons — work with reach across the UK ecosystem, not confined to a single lab.
- It is a deliberate platform to launch from. The post is designed to let you build a visible, fundable independent research identity and the track record to launch it — whether toward a research fellowship (RAEng, UKRI FLF, MSCA, ERC Starting), a first permanent academic appointment, or a senior role in the national semiconductor ecosystem. The four-year term gives genuine room to figure out which of those is right for you and to become competitive for it.
- You will be a named representative of CHIMES² externally — at IMAPS, IEEE ECTC, TechWorks DESN and equivalent forums — and a named author on Design Commons white papers, capability maps and policy briefings produced from your work.
- Advanced packaging architectures — 2.5D silicon interposer, 3D hybrid bonding, fan-out WLP/PLP, glass interposers — and their physical-design implications.
- Back-end EDA and physical implementation for multi-die stacks — place-and-route, cross-die DRC/LVS, packaging parasitics extraction, packaging-aware timing and signal/power-integrity sign-off.
- Known-good-die test methodology and its relationship to physical implementation; reliability, qualification and manufacturing yield.
- The UK and global supply chain for HI — OSAT and foundry pathways, compound-semiconductor assembly and its interface with silicon back-end processes.
- Sustainability, lifecycle assessment and embodied‑carbon modelling applied to packaging and assembly.
All four cross-cutting constraints — design-for-test (DfT), design-for-power-delivery (DfP), design-for-security (DfS) and design-for-thermal-extraction (DfTh) — span the logical-physical boundary, and both post holders are expected to develop working familiarity with them regardless of primary domain.
No candidate need span all areas. Strong credibility in one area of advanced packaging, semiconductor test, back-end physical implementation, or supply‑chain analysis is the core requirement; depth in one or more of the complementary areas above is welcomed.
We particularly welcome applicants whose work has bridged from adjacent backgrounds — materials, devices, sensors, photonics, RF, power electronics (GaN/SiC), or board‑level integration — into packaging, assembly, test and integration work. To be clear, the focus is on the systems-and-integration direction; candidates whose current work is still on the device‑physics or process side are out of scope for this post, as that capability is well covered elsewhere in the QSS Group, through CHIMES² partners (notably Imec), and through national semiconductor programmes.
- Lead WP1 Activities: Direct structured landscape analyses mapping integrator needs for maturing‑TRL devices, circuits, and interposers across back‑end EDA capability, advanced packaging architectures, and manufacturing transitions.
- Maintain CHIMES² Roadmaps: Develop physical implementation and manufacturing roadmaps (EDA gaps, known‑good‑die test, reliability, yield) benchmarked against IEEE HIR, EU APECS, DARPA NGMM, JEDEC, IPC, SEMI, and EDA vendor roadmaps (Siemens, Synopsys, Cadence).
- Analyze Heterogeneous Integration (HI) Gaps: Evaluate HI EDA gaps (cross‑die timing closure, DfT test access, DfP/backside power delivery, DfTh thermal extraction, and tamper‑evident physical security).
- Logical‑to‑Physical Handoff: Perform gap analysis where physical execution fails architectural intent (parasitic extraction, packaging‑aware sign‑off) to inform Design Commons guidance.
- Represent & Network: Act as CHIMES² ambassador at global forums (iMAPS, IEEE ECTC, TechWorks DESN), engaging OSATs, foundries, EDA vendors, standards bodies (UCIe), and UK agencies (CSA Catapult, NEF, NPL).
- Policy & Strategy: Contribute technical intelligence to government consultations, policy briefings, Advisory Boards, and companion RIF initiatives.
- Programme Synthesis: Work across domain‑specific CHIMES² leads to aggregate research college inputs into coherent roadmap assets, collaborating with the companion RIF on logical‑to‑physical handoff methodologies.
- Internal Integration: Partner with the Sheffield engineering team to feed demonstrator programs, support skills‑building, and synthesize research into unified roadmap assets.
- Deliverables & Guidance: Author Design Commons white papers, capability maps, and WP3 demonstrator briefs aligned with international benchmarks (SRC JUMP 2.0, EU Chips JU).
- Independent Research: Establish a high‑impact research theme in heterogeneous integration to build toward future fellowship or academic applications.
- Academic Output: Co‑author peer‑reviewed publications, present at major conferences, and contribute domain intelligence to secure future funding extensions.
- Independent Research: Establish a CHIMES²‑aligned research theme in heterogeneous integration, endorsed by the Director, to form the basis for future fellowship or first‑academic‑post applications.
- Publishing & Authorship: Serve as named author on Design Commons assets and policy briefings, developing them into peer‑reviewed outputs and conference presentations.
- Academic Translation: Collaborate with Co‑Investigators and PDRAs to keep landscape work grounded in research frontiers and contribute intelligence to future funding applications and extensions.
- Carry out other duties, commensurate with the grade and remit of the post
Our community welcomes diverse backgrounds and experiences. We particularly encourage applications from researchers in their first postdoctoral position, and from researchers in a second postdoctoral role who would prefer a post of this kind to moving directly to a lectureship and from candidates whose work has bridged from adjacent backgrounds (materials, devices, sensors, photonics, RF, quantum hardware, FPGA, embedded systems, or high‑speed PCB / board‑level integration) into circuit, system and integration work. Even if your past experience doesn’t match perfectly with this role’s criteria, your contribution is valuable and we encourage you to apply. Please ensure that you reference the application criteria in your application statement.
Applicants Must Provide The Following Documents When Making Their Application — Please Upload a Merged PDF Document Under The Cover Letter Section On Our Application System:
- CV (including a list of publications and / or technical outputs).
- A Research Vision Statement, setting out the independent research direction you would develop in this post and how it intersects with CHIMES²’s heterogeneous‑integration mission — written so that it could form the seed of a future fellowship or first‑academic‑post application.
- A statement of up to three best outputs (peer‑reviewed publications, or for candidates from industry, technical reports, standards contributions, or product / roadmap documentation that demonstrate the ability to produce high‑quality written intelligence). For one of these, provide a short statement of no more than 100 words describing its originality, significance and rigour.
- Technical credibility in the physical implementation, advanced packaging, test or supply‑chain domain (the primary shortlisting filter).
- Ability to synthesise and communicate complex technical intelligence to specialist and non‑specialist audiences (the primary differentiator at interview, alongside technical depth).
- A credible, articulated independent research vision that intersects with CHIMES²’s mission.
- Ability to work across academic and industrial environments and to represent a national programme externally.
The full criteria are listed in the table below. No candidate need span all areas: we are looking for strength in the core domain competence plus depth in one or more of the named complementary areas.
Hold or be close to completing a PhD in electrical and electronic engineering, materials science (with strong systems‑level context), manufacturing engineering or a closely related discipline with demonstrable expertise in one or more of: advanced packaging or semiconductor assembly; chiplet‑or wafer‑level test; semiconductor supply‑chain analysis; reliability and qualification; or HI manufacturing processes. Equivalent industrial R&D experience is also considered
familiarity with at least one of: back-end EDA flows for multi‑die design (place‑and‑route, physical verification, cross‑die DRC/LVS, cross‑die timing closure); advanced packaging architectures (2.5D Si interposer, 3D hybrid bonding, fan‑out WLP/PLP, glass interposers) and their physical‑design implications; known‑good‑die test methodology; packaging‑aware signal and power integrity; or compound-semiconductor assembly and its interface with silicon back‑end processes.
of RTL, synthesis, floorplanning and of how logical design decisions constrain physical implementation, packaging selection and manufacturing yield for HI systems.
Awareness of design-for-test (e.g. IEEE 1838 3D-IC test, known‑good‑die implications), design-for-power-delivery (UPF/CPF power intent, IVR strategies, backside power delivery), design-for-security (hardware root‑of‑trust, chiplet attestation, secure supply chain, side‑channel considerations) and design-for-thermal extraction (thermal‑aware floorplanning, TIM selection, embedded cooling, junction‑temperature budgeting). Working familiarity with all four is expected regardless of primary specialism.
Experience with back‑end / physical implementation EDA tools (e.g. Cadence Innovus, Synopsys ICC2 / Fusion Compiler, Siemens Calibre, Ansys RedHawk or equivalent) and their extension to multi‑die HI contexts, including cross‑die DRC/LVS and packaging parasitics.
Demonstrable ability to synthesise complex technical and ecosystem intelligence into high‑quality written outputs accessible to technical and non‑specialist audiences — policy briefings, landscape reports, capability maps, white papers, or equivalent industry deliverables. Industry candidates may evidence this through technical reports, roadmap documentation or standards contributions.
A credible, articulated independent research vision that intersects with (rather than runs parallel to) CHIMES²’s heterogeneous‑integration mission, with the potential to develop into fellowship or first‑academic‑post applications.
Experience of sustainability analysis, lifecycle assessment or embodied‑carbon modelling applied to semiconductor packaging and assembly.
Evidence of external engagement — conference presentations, cross‑institution collaboration, or equivalent industry engagement — and the ability to represent an organisation professionally in technical and policy forums.
Active engagement in external networks, consortia or working groups, contributing to jointly authored recommendations, standards submissions, roadmap assets or other collective outputs.
Strong written and verbal communication; ability to work independently across multiple workstreams; ability to work across academic and industrial environments; commitment to equality, diversity and inclusion.
Experience of mentoring, supervising or line‑managing early‑career researchers or PGR students.
Track record of contributing to successful external research funding applications, as named investigator or equivalent. Candidates from industry may evidence this through authorship of successful internal investment cases, product or programme proposals, or change proposals that secured funding, headcount or executive approval.
Experience of representing an organisation at national or international level in policy, standards or advisory forums — government consultations, advisory boards, standards bodies, or equivalent industry and professional groupings.
7
Grade 7: £38,784-£47,389
Full time; Hybrid and flexible working options considered
Fixed term for 48 months (4 years) from start date
Professor John Goodenough, CHIMES² Director / PI
If you do not currently hold the right to work in the UK, you can find more information here to help determine your visa eligibility. Additional guidance is also available on the UK Visa & Immigration website.
https://www.sheffield.ac.uk/eee
For informal enquiries about this job contact Prof John Goodenough, CHIMES² Director / PI: n.j.goodenough@sheffield.ac.uk
It is anticipated that the selection process will take place on week commencing 16/11/26 This will consist of an interview and a presentation. We plan to let candidates know if they have progressed to the selection stage on the week commencing 09/11/26. If you need any support, equipment or adjustments to enable you to participate in any element of the recruitment process you can contact eee-operations@sheffield.ac.uk.
We are the University of Sheffield. This is our vision: sheffield.ac.uk/vision (opens in new window).
- A minimum of 41 days annual leave including bank holiday and closure days (pro rata) with the ability to purchase more.
- Flexible working opportunities, including hybrid working for some roles.
- Generous pension scheme.
- A wide range of discounts and rewards on shopping, eating out and travel.
- A variety of staff networks, providing opportunities for social interaction, peer support and personal development (for example, Race Equality, LGBT+, Women’s and Parent’s networks).
- Recognition Awards to reward staff who go above and beyond in their role.
- A commitment to your development access to learning and mentoring schemes.
- A range of generous family-friendly policies
- paid time off for parenting and caring emergencies
- support for those going through the menopause
- paid time off and support for fertility treatment
- and more
More details can be found on our benefits page: sheffield.ac.uk/jobs/benefits (opens in a new window).
We are a Disability Confident Employer. If you have a disability and meet the essential criteria for this job you will be invited to take part in the next stage of the selection process.
Some activities associated with this post may require the postholder to undertake a Government baseline personnel security standard (BPSS) check — for example where landscape or roadmap work extends into defence-related areas. This is not a condition of appointment; where it applies, the University will support the postholder through that process.
Closing Date : 01/11/2026
We are a research university with a global reputation for excellence. Our ideas and expertise change the world for the better, making a real difference to society. We know that when people come together with different views, approaches and insights it can lead to richer, more creative and innovative teaching and research and the highest levels of student experience. Our University Vision (www.sheffield.ac.uk/vision) outlines our commitment to building a diverse community of staff and students that recognises and values the abilities, backgrounds, beliefs and ways of living for everyone.
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