Process Optimization and Characterization of Tight Pitch Dielectric Etch for CFET MOL Integration

Imec India Private Limited; Cambridge; On-site; GBP 80,000 - 100,000; Full time

Job summary

A leading semiconductor research institute in Cambridge is seeking an intern to work on CFET MOL dielectric etch process development. The role focuses on investigating etching challenges, evaluating chemistries, and using advanced analytical techniques. Ideal candidates should have a Master's degree in relevant fields and an interest in semiconductor technology. This internship lasts for one year and is a combination of project work and thesis.

Qualifications

• Master's degree in Chemistry, Chemical Engineering, Materials Engineering, Nanoscience & Nanotechnology, or Physics.
• Experience with etching processes and semiconductor fabrication.
• Strong analytical skills to assess etching impacts.

Responsibilities

• Develop CFET MOL dielectric etch processes.
• Investigate etching process challenges across different pitches.
• Evaluate plasma etch chemistries and strategies.

Skills

Dielectric etch process development

Analytical skills

Plasma etch chemistries

Understanding of semiconductor devices

Education

Master of Science or Master of Engineering Science

Tools

SEM/CD-SEM

TEM analysis

Job description

Summary of Research Project

As the semiconductor industry moves beyond FinFETs toward Complementary FETs (CFETs) to enable continued transistor scaling, the Middle of Line (MOL) interconnect region faces new challenges. CFET requires tight-pitch dielectric etching to integrate vias and contacts in vertically stacked N/P devices. The project aims to investigate and optimize dielectric etch processes for ≤50nm pitch CFET middle-of-line (MOL) integration.

The reliability and performance of CFET devices depend on the etch process quality in these dense regions, especially:

1. Minimizing etch-induced damage to underlying or adjacent features.
2. Maintaining critical dimension (CD) control and profile control.
3. Achieving high anisotropy with low line edge roughness (LER).
4. Etch process selectivity to hardmask and spacer material etc.

The intern will work on:

• CFET MOL dielectric etch process development at pitch 60nm and 50nm – Dep/Etch cyclic etch process vs. QALE (quasi atomic layer etching).
• Understanding and compare etching process challenges for two different pitch – 60nm vs. 50nm (or even smaller, for example 42nm).
• Investigating hardmask and spacer strategies to enable tight pitch fidelity.
• Evaluating plasma etch chemistries (e.g., fluorocarbon-based, H2/N2-based) for high anisotropy and selectivity.
• Evaluating low temperature (cryo) plasma etch benefit compared to conventional etch process.
• Studying etch-induced damage and its impact on downstream metallization.
• Using SEM/CD-SEM and TEM analysis to assess profile, CD, and etch residue.

Type of Project: Combination of internship and thesis

Master's degree: Master of Science; Master of Engineering Science

Master program:Chemistry/Chemical Engineering; Materials Engineering; Nanoscience & Nanotechnology; Physics

Duration: 1 year

For more information or application, please contact the supervising scientist Tanushree Sarkar ([e-mail]).