Principal Software Engineer

weeteq; Glasgow; On-site; GBP 110,000 - 140,000; Full time

Job summary

weeteq is seeking a Principal Software Engineer to architect the firmware and SDK for weeteq and third-party MCUs, overseeing timing and telemetry pipelines in real-time, silicon-close systems.

This senior, hands-on leadership role sets the technical direction, mentors engineers, and drives end-to-end development from architecture to delivery across FPGA and RTOS environments.

Qualifications

• Expert-level C/C++ for real-time targets.
• Experience with RTOS such as Zephyr or FreeRTOS.
• Silicon-close development from concept to chip.
• Familiarity with FPGA toolchains and timing validation.

Responsibilities

• Set technical direction — own the architecture and engineering standards across embedded, real-time and ML-on-device workstreams.
• Mentor and technically line-manage a growing team, set quality bar, review critical code.
• Be the senior voice — represent software in leadership decisions, roadmap planning and due diligence with customers and partners.
• Deliver hands-on — stay close to the code and unblock the team, personally own the hardest problems.

Skills

C / C++

RTOS

Embedded systems

System-level design

DSP / ML on device

Tools

Zephyr

FreeRTOS

Vivado

Job description

weeteq builds real-time power and control intelligence. We're hiring a Principal Software Engineer to architect the firmware and SDK for weeteq and third-party MCUs — the timing and telemetry pipelines that manage hardware-level state transitions and system-level optimisation under dynamic AI workloads.

This is a senior, hands-on leadership role. You set the technical direction for our software, lead the engineers who build it, and own the development process end to end: architecture through delivery on silicon-close, real-time systems. You'll lead development of highly optimised RTOS environments, design the APIs for system-level integration, and drive pre-silicon validation on FPGA.

The mandate: lead the software development, own the process. You are the expert accountable for how we design, build and validate the code that runs inside the control loop.

Leading the software

• Set technical direction — own the architecture and engineering standards across embedded, real-time and ML-on-device workstreams, and make the hard build-versus-buy calls.
• Lead the engineers — mentor and technically line-manage a growing team (today 8 technical staff plus contractors), set the quality bar, review critical code, grow people into their next level.
• Be the senior voice — represent software in leadership decisions, roadmap planning and technical due diligence with customers, partners and investors.
• Deliver hands-on — stay close to the code, unblock the team, personally own the hardest problems.

Owning the process

• Define how we build — the full lifecycle: architecture, coding standards, version control, code review, CI/CD, testing, release management.
• Engineer for real-time — the verification, validation and traceability practices demanded by safety- and timing-critical embedded systems.
• Drive quality and cadence — delivery predictability, technical debt, tooling and documentation as the team scales.
• Bridge hardware and software — partner with silicon and systems engineering from concept to chip.

What you’ll build

• Ultra-lightweight microkernel RTOS environments (Zephyr / FreeRTOS) tuned for sub-millisecond loops, with hard real-time, zero-jitter scheduling across high-frequency I3C timing transitions.
• Developer-facing HALs and secure APIs exposing I3C hardware blocks to the BMC.
• Low-latency telemetry pipelines capturing voltage, current and temperature at microsecond intervals, and interrupt-driven firmware that parses events such as sudden dI/dt spikes from AI training and inference state shifts.
• Predictive power management via I3C In-Band Interrupts, preventing server throttling.
• Hardware-in-the-loop firmware on FPGA emulation platforms (Xilinx UltraScale+, Intel Stratix / Agilex), RTL co-verification with digital design, and timing validation using Vivado ILA / SignalTap.

What you bring

• Expert-level C / C++ for resource-constrained, real-time targets, with a strong grasp of DSP, control systems or on-device ML.
• RTOS mastery — custom drivers, memory management and thread schedulers in Zephyr, FreeRTOS or proprietary real-time microkernels.
• Systems thinking: comfortable silicon-close, across the hardware/software boundary, from concept to chip.
• Familiarity with the power profiles, sideband management needs and OCP standards governing AI accelerator clusters and GPUs.
• Hands‑on FPGA toolchains — flashing, debugging and running embedded software on bare‑metal prototypes.
• Technical leadership — you set direction, lead the engineers, and own the development process end to end.

Why weeteq

Own the software function of a fabless semiconductor company at the moment it scales — genuine principal-level scope. Work on a real industry problem: the AI power crisis, the 800V transition, and the transients legacy control can't handle. Proven traction — OCP best-paper winner, test chip in hand, cash-flow positive, Silicon Catalyst and Arm partners.