Principal RTL Design Engineer

Yoh; Chilworth; Hybrid; GBP 100,000 - 125,000; Full time

Job summary

A leading deep-tech company in Southampton is seeking a Lead FPGA Design Engineer for its innovative satellite communications technology. The role involves shaping and delivering complex RTL designs while mentoring junior engineers in a collaborative environment. The ideal candidate should have extensive experience with Verilog or SystemVerilog and a strong track record in high-throughput FPGA or ASIC IP deliveries. This position offers a competitive salary, equity, and a supportive hybrid working setup.

Benefits

Competitive salary

Equity

Private medical

Pension

Relocation support

Qualifications

• Extensive experience developing complex digital designs in Verilog or SystemVerilog.
• Strong track record delivering high-throughput FPGA or ASIC IP.
• Expertise in simulation, synthesis, timing optimisation, and lab-based validation.

Responsibilities

• Lead key projects and mentor junior engineers.
• Drive the development of optimised, production-ready IP for advanced Layer 1 systems.
• Influence product direction and engineering methodology.

Skills

Verilog or SystemVerilog

FPGA or ASIC IP delivery

Simulation and synthesis expertise

UVM-based verification proficiency

Project leadership

Collaboration across disciplines

Tools

EDA tools

Job description

Lead FPGA Design Engineer - Space-Based 5G Communications

Location: Southampton, UK (Hybrid)

Package: Competitive base salary + equity + pension + private medical + relocation support / visa

A well‑funded, fast‑growing deep‑tech company is developing high‑performance signal processing technology for deployment onboard satellites.

They are looking to appoint a Lead FPGA Design Engineer to take a central role in shaping and delivering complex RTL designs for FPGA (and ASIC) targets. This is a senior, hands‑on role where technical excellence and delivery ownership go hand in hand. The successful candidate will lead key projects, mentor junior engineers, and drive the development of optimised, production‑ready IP for advanced Layer 1 systems.

This is a rare opportunity to join a high‑calibre team working at the forefront of next‑generation satellite communications, with significant scope to influence both product direction and engineering methodology.

What they're looking for:

• Extensive experience developing complex digital designs in Verilog or SystemVerilog
• Strong track record delivering high-throughput FPGA or ASIC IP, ideally in signal processing or comms applications
• Expertise in simulation, synthesis, timing optimisation, and lab‑based validation
• Proficiency with industry-standard EDA tools and UVM-based verification
• Ability to lead projects, define architecture, and support junior engineers
• Comfortable collaborating across hardware, software, and systems disciplines
• Space or satellite comms experience is not essential—but curiosity and a builder's mindset are highly valued

Why consider this opportunity:

• Join a collaborative, low-bureaucracy environment where your technical input has real impact
• Help build mission‑critical technology powering global communications from space
• Take on a high‑trust role with strong influence over architecture and engineering direction
• Enjoy a competitive salary, meaningful equity, and a supportive hybrid work setup
• Excellent benefits including private healthcare and pension

Interested? Please apply with your CV or get in touch to arrange a confidential discussion