Principal Analog Layout Engineer

Chipright; United Kingdom; Remote; GBP 60,000 - 80,000; Full time

Job summary

A leading semiconductor firm is seeking a Principal Analog Layout Engineer with a minimum of 5 years of experience. The role involves designing critical timing layouts and matching techniques for sophisticated circuits. Proficiency in Cadence tools like PVS, QRC, and Pegasus is required. Candidates with experience in 65nm technology are particularly desirable.

Qualifications

• Minimum 5 years experience in Analog Layout Engineering.
• Experience in 65nm technology and below, ideally 22nm.
• Understanding of critical timing layouts and matching techniques.

Responsibilities

• Design and optimize analog layouts for integrated circuits.
• Work on critical timing circuits and oversee chip finishing.

Skills

Analog Layout Design

Critical Timing Layout

Matching Techniques

Tools

Cadence PVS

QRC

Pegasus

Job description

Principal Analog Layout Engineer- Minimum 5 years experience but ideally >8+ years Experience- experience in 65nm and below(ideally 22nm and below)- understanding of layout for critical timing (PLL, DLL, clock distribution)- understanding of matching techniques for timing circuits and current cells- chip finishing experience a bonus- experience of Cadence PVS/QRC/Pegasus

Senior Analog & AMS Recruitment Specialist