Package Design Engineer - Semiconductors

Technical Futures. Careers; Remote; GBP 80,000 - 100,000; Full time

Job summary

A thriving High Technology firm is seeking an experienced IC Package Design Engineer to lead package design activities. This role requires expertise in Cadence APD/SIP, RLC parasitic extraction, and knowledge of packaging technologies. The ideal candidate will have 5+ years of relevant experience and an Electronic Engineering degree. A highly competitive salary package is offered, with possibilities for remote work from the UK, Switzerland, or Taiwan.

Qualifications

• Proven top level Package design and RLC parasitic extraction.
• 5+ years in IC Package design using Cadence APD / SIP.
• Using Cadence (Virtuoso / Extract IM / Power DC) / Ansys / SQW Tools (SiWave / Q3D).
• Using AutoCAD tool.
• Knowledge of various IC Packaging technology.
• Electronic Engineering related Degree qualification.
• A basic understanding of Thermal and mechanical behaviour of IC Packages.

Responsibilities

• Undertake all package design activities.
• Ensure cost effective methodologies are incorporated.
• Complete verification of electrical characteristics of the package.
• Provide support to Assembly related activities.

Skills

Proven top level Package design and RLC parasitic extraction

5+ years in IC Package design using Cadence APD / SIP

Using Cadence (Virtuoso / Extract IM / Power DC) / Ansys / SQW Tools (SiWave / Q3D)

Using AutoCAD tool

Knowledge of various IC Packaging technology

Electronic Engineering related Degree qualification

A basic understanding of Thermal and mechanical behaviour of IC Packages

Education

Electronic Engineering related Degree qualification

Tools

Cadence APD

Cadence (Virtuoso / Extract IM / Power DC)

Ansys

SQW Tools (SiWave / Q3D)

AutoCAD

Job description

An IC Package Design Engineer with extensive hands‑on experience using Cadence APD / SIP will join a thriving High Technology scale‑up, enabling the build of scalable, energy efficient AI systems Worldwide.

The IC Package Design Engineer will undertake all package design activities; ensuring cost effective methodologies are incorporated, completing verification of electrical characteristics of the package and providing support to Assembly related activities.

The IC Package Design Engineer should possess the following skills & experience :

• Proven top level Package design and RLC parasitic extraction.
• 5+ years in IC Package design using Cadence APD / SIP.
• Using Cadence (Virtuoso / Extract IM / Power DC) / Ansys / SQW Tools (SiWave / Q3D).
• Using AutoCAD tool.
• Knowledge of various IC Packaging technology.
• Electronic Engineering related Degree qualification.
• A basic understanding of Thermal and mechanical behaviour of IC Packages.

This exciting Semiconductor Company will offer a highly competitive salary package to the successful IC Package Design Engineer. Can be based in UK, Switzerland or Taiwan.

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