Machine Learning Engineer, Compiler

Wayve; Greater London; On-site; GBP 120,000 - 160,000; Full time

Job summary

Wayve in London is seeking a Staff ML Compiler Engineer to own the end-to-end ML compilation pipeline from model checkpoint to deployable bundle on NVIDIA TensorRT and Qualcomm QNN targets. You will design passes, extend precision typing, and build scalable infrastructure to support multiple architectures, while collaborating with model and training teams to ensure accuracy and performance.

This role offers deep ownership, hands-on implementation, and impact on embedded hardware in Wayve's

Qualifications

• Built or owned significant parts of an ML compilation or graph-lowering pipeline.
• Deep experience with multi-stage lowering and debugging per-stage failures.
• Strong Python; C++ is a plus; able to work with vendor backends.

Responsibilities

• Own the ML compilation pipeline end-to-end for targeted hardware.
• Design compiler passes with accuracy and latency gates.
• Extend precision typing and graph-splitting for new architectures.
• Collaborate with model and training teams on compilability.
• Build regression and benchmarking to validate changes across releases.

Skills

Python

Compiler design

Cross-functional communication

Tools

MLIR

ONNX

TensorRT

Qualcomm QNN

PyTorch export/capture

Job description

THE ROLE

Wayve is building autonomous driving technology that runs on real vehicles. Getting our models onto embedded hardware – correctly, quickly, and reproducibly – is one of the hardest problems between research and product. As a ML Compiler Engineer, you will own the compilation pipeline that makes that possible. You will build and extend Wayve's ML compiler end-to-end: designing passes, integrating with vendor toolchains like NVIDIA TensorRT and Qualcomm QNN, and delivering deployable bundles that meet our accuracy and latency requirements on every target platform. Each stage in the pipeline – capture, decomposition, precision assignment, legalisation, partitioning – can affect accuracy, latency, or whether a vendor backend accepts the graph. Your work spans the full lowering stack, building compiler passes and infrastructure that scale across architectures and target platforms.

KEY RESPONSIBILITIES

• Own the ML compilation pipeline end-to‑end – from checkpoint to deployable bundle on NVIDIA (TensorRT) and Qualcomm (QNN) targets.


• Design and implement compiler passes with accuracy and latency gates, so bad compiles are caught before they reach hardware.


• Build compilation infrastructure that scales across platforms, model architectures, and SoCs – without re‑engineering for each new target.


• Partner with model and training teams on compilability; build regression and benchmarking to validate changes across releases.


• Set technical direction and raise the bar for compiler engineering across the team.

ABOUT YOU

• You have built or significantly extended ML compilation or graph‑lowering pipelines.


• You understand multi‑stage lowering (capture, decomposition, precision assignment, legalisation) and can debug what breaks at each stage.


• Strong proficiency with at least one relevant stack (e.g. MLIR, ONNX, TensorRT, Qualcomm QNN, PyTorch export/capture) and confidence learning adjacent frameworks quickly.


• Experience with quantisation in compilation – precision typing, PTQ integration, and tracking down accuracy loss from compiler transforms.


• Comfortable from high‑level model graphs down to vendor backend constraints; strong Python, with C++ a plus.


• Clear communicator who can align cross‑functional teams on compilation trade‑offs.


• Real compiler ownership – full lowering pipeline from checkpoint to deployable bundle, working deeply with TensorRT and QNN.


• Hard problems – quantisation preservation through decomposition, cross‑SoC precision typing, graph partitioning under speed/accuracy trade‑offs, legalisation that does not silently break earlier passes.


• Vehicle impact – compiler passes determine what runs on embedded hardware in Wayve's driving product.


• Greenfield at Staff level – small team, high leverage, shaping the compilation stack from early stages.


• Scalable infrastructure – building pipelines that work across platforms and architectures without starting from scratch each time.

Day‑to‑day / scope of the role

• Own the ML compilation pipeline end-to‑end on NVIDIA (TensorRT) and Qualcomm (QNN) targets.


• Design and implement compiler passes with accuracy and latency gates.


• Extend precision typing and graph‑splitting logic for new architectures and SoCs.


• Partner with model and training teams on compilability.


• Build regression and benchmarking to validate changes across releases.


• Set technical direction and mentor on compiler design.

Top hard requirements (skills/experience)

• Built or owned significant parts of an ML compilation or graph‑lowering pipeline.


• Deep experience with quantisation in compilation – precision typing, PTQ integration, debugging accuracy loss from compiler transforms.


• Strong Python – comfortable building and testing compiler infrastructure in production codebases.


• Proficiency with at least one of: MLIR, ONNX, TensorRT, Qualcomm QNN, PyTorch graph capture/export.


• Experience with multi‑target compilation or graph partitioning across hardware backends.


• Ability to reason about correctness and performance trade‑offs at each compiler stage.