Lead Probabilistic Compute ASIC Architect

Redline Group Ltd; Oxford; On-site; GBP 90,000 - 140,000; Full time

Job summary

Redline Group Ltd. is seeking an experienced ASIC Architect to own the end-to-end architecture of a probabilistic computing processor. You will define system ISA and dataflow, perform HW/SW co-design, and drive simulations and models to steer architectural decisions toward tape-out and silicon bring-up.

The role requires hands-on architectural leadership, verification strategy input, and collaboration with firmware and compiler teams to deliver a cutting-edge compute accelerator.

Qualifications

• ,Own end-to-end ASIC architecture from algorithm to tape-out.

Responsibilities

• Own the end-to-end ASIC architecture of a probabilistic computing processor, from algorithm understanding through to tape-out.
• Define system architecture, ISA and dataflow models based on workload requirements.
• Perform HW/SW co-design activities, including arithmetic implementation and analysis of programmability and host requirements.
• Build functional simulations and performance models to guide architectural decisions.
• Conduct timing, power and area trade-off analysis with strong physical design awareness.
• Define detailed microarchitecture specifications, including memory hierarchy, connectivity and interface requirements.
• Lead internal IP development and evaluate third-party IP solutions.
• Guide designs through verification, sign-off, tape-out and silicon bring-up.

Skills

ASIC ownership

Performance modelling

Python/C++

EDA tool flows

Timing/Power/Area

HW/SW co-design

RTL verification

Interface definitions

Tools

Synopsys

Cadence

Siemens EDA

Job description

Redline Group Ltd. is seeking an experienced ASIC Architect to own the end-to-end architecture of a probabilistic computing processor. You will define system ISA and dataflow, perform HW/SW co-design, and drive simulations and models to steer architectural decisions toward tape-out and silicon bring-up.

The role requires hands-on architectural leadership, verification strategy input, and collaboration with firmware and compiler teams to deliver a cutting-edge compute accelerator.