Hardware Verification Engineer

Baya Systems; Liverpool; On-site; GBP 60,000 - 85,000; Full time

Job summary

A tech company in the UK is seeking a seasoned Design Verification designer to shape their technology portfolio. The candidate will collaborate with design teams to create complex test plans and write UVM/SystemVerilog code. With a focus on block-level and SOC-level verification, applicants should have 8+ years of experience and be proficient in Verilog and SystemVerilog. Strong communication skills and a collaborative mindset are essential for this role.

Qualifications

• 8+ years of hands-on experience in block-level/IP-level/SOC-level verification.
• Proficient in Verilog and SystemVerilog.
• Experience with ARM AMBA protocols such as AXI, APB, and AHB.

Responsibilities

• Collaborate with design and architecture teams to create test plans.
• Write UVM/SystemVerilog code to implement test plans and checkers.
• Collaborate with software teams to implement configurable testbenches.

Skills

Verilog

SystemVerilog

Python

UVM-based testbenches

Communication skills

Collaborative skills

Education

BS / MS in Electrical Engineering

Computer Engineering

Computer Science

Tools

EDA tools

Job description

About the Role : We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions.

Responsibilities

• Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems
• Write UVM / SystemVerilog code to implement the test plan, checkers and scoreboards
• Collaborate with software teams to define and implement configurable testbenches
• Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Qualifications

• BS / MS in Electrical Engineering, Computer Engineering or Computer Science
• 8+ years and current hands‑on experience in block‑level / IP‑level / SOC‑level verification
• Proficiency in Verilog, SystemVerilog
• Familiarity with industry‑standard EDA tools for simulation and debug
• Deep experience with UVM‑based testbenches
• Experience with modern programming languages like Python
• Knowledge of ARM AMBA protocols such as AXI, APB, and AHB
• Understanding of ARM CHI protocol is a plus
• Experience working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs
• Experience with formal verification techniques and emulation platforms is a plus
• Excellent problem‑solving skills and attention to detail
• Strong communication and collaboration skills