Hardware Verification Engineer

Intellectual Capital Resources Ltd; Cambridgeshire and Peterborough; In loco; GBP 65.000 - 90.000; Tempo pieno

Descrizione del lavoro

Intellectual Capital Resources Ltd in Cambridge is seeking a Senior Verification Engineer to join a rapidly growing HW team. You will work on cutting-edge technology in quantum computing and learn alongside world-class engineers in a cross-disciplinary environment.

You will own verification across block, subsystem, and multi-FPGA designs, develop scalable UVM testbenches and define the verification strategy in collaboration with the Lead Verification Engineer.

Competenze

• Strong SystemVerilog and UVM expertise.
• Debug across RTL, simulation, and hardware.
• Ability to work with ambiguity and changing requirements.
• Commercial experience in functional verification including planning/strategy.
• Exposure to C, C++ and Python.
• Formal verification experience (plus).
• Experience mentoring junior verification engineers.

Mansioni

• Own the verification strategy across block, subsystem, and multi-FPGA designs.
• Develop scalable UVM-based testbenches that push boundaries.
• Drive verification efforts with a focus on risk, coverage, and system-level behavior.

Conoscenze

SystemVerilog

UVM

RTL Debugging

Verification planning & strategy

C/C++/Python exposure

FPGA Verification

Mentoring

Descrizione del lavoro

I am seeking a Senior Verification Engineer to join a rapidly growing HW Team in Cambridge. You will get the opportunity to work on cutting edge technology and in the area of quantum computing. No prior experience in quantum computing? No problem. You'll learn as you go while working alongside world-class engineers in a truly cross-disciplinary environment.

As a Senior Verification Engineer, you will take ownership of verification across block, subsystem, and multi-FPGA system-level designs.

With visibility across the entire stack, you will partner closely with the Lead Verification Engineer to define and deliver the verification strategy.

As a key member of the verification team, you will:

• Own the strategy and execution for block-level, subsystem, and multi-FPGA system designs
• Develop scalable UVM-based testbenches that push boundaries
• Drive verification efforts with a sharp focus on risk, coverage, and system-level behaviour

Key skills

• Strong hands-on expertise in SystemVerilog and UVM
• Proven ability to debug across RTL, simulation, and hardware
• Ability to work effectively with ambiguity and changing requirements
• Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy
• Exposure to different programming languages, such as C, C++ and Python
• Formal verification experience(plus)
• Experience mentoring junior verification engineers

The salary range for this role is broad, as they are able to consider varying levels of experience.

For more information contact Rachel Mason at IC Resources.