FPGA Digital Design Engineer - Lab-Driven RTL & DSP

SoCode Recruitment; Cambridge; On-site; GBP 55,000 - 85,000; Full time

Job summary

SoCode Recruitment is seeking an engineer to own RTL blocks for FPGA platforms, from specification through implementation and verification, in a close-knit team. You will work alongside senior engineers and gain hands-on lab time with advanced equipment.

The role emphasizes learning, effective communication within a small team, and growth across digital RF and DSP concepts in a well-equipped lab environment.

Qualifications

• 2+ years of RTL development for FPGA platforms (Verilog or VHDL).
• Strong fixed-point DSP concepts (filters, FFTs).
• Experience with AMD/Xilinx FPGA toolchains and devices.
• End-to-end design from spec to hardware validation.

Responsibilities

• Own significant blocks of RTL from specification through implementation and test.
• Collaborate with senior/principal engineers to broaden experience.
• Engage in hands-on lab work and use serious test equipment.

Skills

RTL development

Verilog/VHDL

Fixed-point DSP

Xilinx/AMD FPGA

Full cycle design

Codebase adaptation

Team communication

Continuous learning

Tools

MATLAB

C/C++

Job description

SoCode Recruitment is seeking an engineer to own RTL blocks for FPGA platforms, from specification through implementation and verification, in a close-knit team. You will work alongside senior engineers and gain hands-on lab time with advanced equipment.

The role emphasizes learning, effective communication within a small team, and growth across digital RF and DSP concepts in a well-equipped lab environment.