Formal Verification Engineer

Technical Futures Ltd; Great Houghton; Hybrid; GBP 70,000 - 90,000; Full time

Job summary

A leading High-Tech company in the UK seeks a Formal Verification Engineer to verify complex FPGA or ASIC designs in the semiconductor industry. The role involves developing verification methodologies, participating in RTL design reviews, and preparing design verification plans. Candidates should have a Bachelor's/Master's in Electronics, 5+ years in the industry, scripting skills, and familiarity with verification techniques. A competitive salary and hybrid working environment are offered.

Benefits

Competitive salary

Career development opportunities

Hybrid working

Qualifications

• 5+ years' experience in the semiconductor industry.
• Proven experience in verifying complex designs - FPGA or ASIC.
• In-depth understanding of formal verification techniques.

Responsibilities

• Develop formal verification methodologies.
• Participate in RTL design reviews.
• Prepare design verification plans and track design bugs.

Skills

Formal Verification techniques

Scripting skills (Python, Perl or TCL)

Metrics-driven verification

Temporal logic assertion languages (SVA, PSL)

Working with RTL designers

Education

Bachelors / Masters Degree in Electronics

Tools

Cadence JasperGold

VManager

Job description

Great opportunity for a Formal Verification Engineer with a proven track record of verifying complex FPGA or ASIC designs within the Semiconductor industry. You'll play a key role in an innovative High-Tech company revolutionizing wired connectivity and pushing the boundaries of AI related innovation. A great salary package will be offered with Hybrid working and career development opportunities.

Skills and experience for the Formal Verification Engineer should include:

• Bachelors / Masters Degree in Electronics related discipline.
• 5+ years' experience of working within the semiconductor industry.
• Proven experience in the Verification of complex designs - FPGA or ASIC.
• Good scripting skills (Python, Perl or TCL for automation).
• Working with RTL designers to develop a formal micro-architecture specification.
• In-depth understanding of Formal Verification techniques.
• Strong knowledge on Metrics-driven verification including test planning and coverage closure.
• Proficiency in temporal logic assertion based languages such as SVA or PSL.

Of particular interest is knowledge of Cadence JasperGold and VManager and familiarity with SerDes and high level protocols.

The successful Formal Verification Engineer will take responsibility for developing formal verification methodologies; participating in RTL design reviews, preparing design verification plans as well as tracking and closing design bugs