Digital Design Engineer

Synopsys, Inc.; Brackley; On-site; GBP 90,000 - 110,000; Full time

Job summary

A leading technology firm in the UK is seeking a digital design engineer to drive innovation in DDR technologies. The role requires at least 15 years of experience, deep expertise in RTL design, and the ability to collaborate effectively with diverse teams. Responsibilities include defining micro-architecture, designing RTL code, and ensuring high-quality output in a fast-paced environment. This position offers a unique opportunity to contribute to cutting-edge technology solutions that shape the future.

Qualifications

• 15+ years of digital design experience.
• Strong knowledge of JEDEC standards.
• Ability to mentor junior engineers.

Responsibilities

• Define micro-architecture at block level.
• Design RTL code according to coding styles.
• Collaborate with verification teams.

Skills

RTL design

DDR technologies

Micro-architecture definition

Scripting (Shell, Perl, Python, TCL)

Problem-solving

Collaboration

Education

MSEE or higher

Tools

Back-end synthesis tools (DC/PT)

Job description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly motivated and innovative digital design engineer with a solid foundation in DDR technologies and a passion for pushing the boundaries of SoC integration. With at least 5 years of industry experience and an advanced degree in electrical engineering, you have developed strong skills in RTL design, micro-architecture definition, and a deep understanding of digital IP design methodologies. Your expertise spans the latest DDR standards, including DDR5, LPDDR5, and HBM4, and you bring valuable knowledge of AXI, CHI, CRYPTO, and RAS protocols.

You thrive on tackling dynamic challenges and adapting to rapid technological advancements. Collaboration is at the heart of your approach, as you work seamlessly with verification teams, application engineers, and customer support groups. Your communication skills enable you to bridge design and support teams, ensuring successful project outcomes and customer satisfaction. You are self-motivated, proactive, and committed to delivering high-quality designs under tight deadlines. You enjoy mentoring junior colleagues and networking with senior experts, contributing to a culture of learning and innovation.

Your curiosity drives you to explore new technologies and best practices, and you leverage your scripting skills in Shell, Perl, Python, and TCL to automate and optimize design flows. You understand the importance of inclusion and diversity, and you value working in an environment that celebrates different perspectives and backgrounds. Your analytical mindset and problem-solving abilities make you a trusted resource for your team and a key contributor to Synopsys’ reputation for excellence.

What You’ll Be Doing:

• Defining micro-architecture at block level based on IP architecture and JEDEC specifications.
• Designing RTL code according to predefined coding styles, including SVA, and ensuring clean code through lint, CDC, DFT, and synthesis checks.
• Collaborating with verification teams to debug and resolve RTL issues for successful IP releases.
• Executing performance testing and supporting functional design from specification through release.
• Utilizing back-end synthesis tools (DC/PT) to optimize designs for performance, power, and area.
• Guiding junior engineers and networking with senior personnel to share knowledge and best practices.
• Interacting with application engineers and customer support teams to address technical challenges and ensure customer satisfaction.
• Continuously learning and exploring new technologies to keep Synopsys solutions at the cutting edge.

The Impact You Will Have:

• Accelerating integration of advanced capabilities into SoCs for industry-leading applications.
• Enhancing performance, power, and size optimization for customer products.
• Reducing risk and time-to-market through robust, innovative digital IP design.
• Contributing to differentiated customer solutions in automotive, AI, cloud, 5G, and IoT domains.
• Ensuring reliability and quality in silicon IP releases through rigorous design and verification.
• Supporting Synopsys’ position as the provider of the world’s broadest silicon IP portfolio.

What You’ll Need:

• MSEE or higher, plus a minimum of 15 years of digital design experience in the industry.
• Strong knowledge of DDR, HBM, and interface technologies, with experience in JEDEC standards.
• Expertise in RTL design, SVA, and back-end synthesis tools (DC/PT).
• Solid foundation in AXI, CHI, CRYPTO, RAS, and AMBA protocols.
• Experience with scripting languages: Shell, Perl, Python, TCL.
• Ability to collaborate with verification teams and application engineers.

Who You Are:

• Self-motivated and proactive, with a drive for high-quality results.
• Excellent communicator, able to interact with diverse design and support teams.
• Strong analytical and problem-solving skills.
• Curious and eager to learn new technologies and methodologies.
• Supportive mentor and collaborative team player.
• Adaptable and resilient in fast-paced, dynamic environments.

The Team You’ll Be A Part Of:

You’ll join a world-class team of digital engineers, working at the forefront of DDR controller design and verification. The team is dedicated to delivering high-end IP solutions, embracing technical challenges, and fostering a culture of innovation and collaboration. You’ll work alongside experts who are passionate about advancing SoC integration and customer success in the Era of Smart Everything.