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ASIC Verification Engineer

Chipright

United Kingdom

Remote

GBP 70,000 - 90,000

Full time

5 days ago
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Job summary

A technology firm in the United Kingdom is seeking a Senior SoC/NoC Verification Engineer. The ideal candidate will lead functional verification of complex SoC designs, with over 10 years of experience and deep expertise in UVM and SystemVerilog. This role involves developing scalable verification environments and mentoring junior engineers. Competitive compensation and opportunities for career growth are offered.

Qualifications

  • 10+ years of hands-on experience in SoC/NoC functional verification.
  • Track record of verifying 7–10 SoCs across multiple technology nodes.
  • Experience with simulation and debug tools.

Responsibilities

  • Lead functional verification of complex SoC designs from specification to tape-out.
  • Develop and maintain UVM-based verification environments.
  • Create test plans, testbenches, and coverage models.

Skills

Deep expertise in UVM
SystemVerilog proficiency
SVA expertise
Strong understanding of AMBA protocols
Debug and root-cause analysis

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Synopsys VCS
Cadence Xcelium
Mentor Questa
Job description
Senior SoC/NoC Verification Engineer

We are seeking a highly experienced SoC/NoC Functional Verification Engineer with a strong background in verifying complex System-on-Chip (SoC) architectures. The ideal candidate will have successfully verified 7–10 SoCs throughout their career and demonstrated deep expertise in UVM‑SystemVerilog-based environments, SVA, and testbench development.

You will play a key technical role in defining verification strategies, building scalable testbenches, driving verification closure, and mentoring junior engineers.

Key Responsibilities
  • Lead and execute functional verification of complex SoC/NoC designs from specification through tape‑out.
  • Develop, enhance, and maintain UVM-based verification environments in SystemVerilog.
  • Create comprehensive test plans, testbenches, assertions (SVA), coverage models, and checkers.
  • Verify and validate AMBA (AXI, AHB, APB), DDR, MIPI, and various peripheral interfaces (JTAG, I²C, SPI, etc.).
  • Perform debug and root‑cause analysis on design and testbench issues, collaborating closely with RTL designers and architects.
  • Define and drive coverage closure strategies to meet verification quality goals.
  • Contribute to verification methodology improvements and automation frameworks.
  • Mentor junior verification engineers and contribute to technical reviews.
Required Qualifications
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of hands‑on experience in SoC/NoC functional verification.
  • Proven track record of verifying 7–10 SoCs across multiple technology nodes or product lines.
  • Deep expertise in UVM (Universal Verification Methodology), SystemVerilog, and SVA (SystemVerilog Assertions).
  • Constrained random and coverage‑driven verification experience.
  • Strong understanding of industry‑standard protocols including AMBA (AXI, AHB, APB), DDR memory interfaces, high‑speed interfaces (MIPI, PCIe, etc.), and peripheral interfaces (JTAG, I²C, SPI, UART, etc.).
  • Experience with simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa) and debug tools.
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