Design Verification Engineer: Master Mixed‑Signal Verification

Texas Instruments; Oulu; On-site; EUR 65,000 - 90,000; Full time

Benefits offered by this job

Career Accelerator Program (CAP)

Job summary

Texas Instruments in Oulu, Finland is seeking a Design Verification Engineer to verify analog and mixed-signal ICs during the design phase. You will develop simulation test benches, automated checkers, and reports for the project team, collaborating across functions to drive defects to closure and increase DV skills with TI's CAP program.

You will work under a senior DV engineer, gain exposure to digital/analog design paths, and contribute to DV strategy and tool improvements for efficient

Qualifications

• Some experience designing electronic circuits and simulating with SPICE or similar tools.
• Familiarity with Verilog or VHDL languages.
• Good spoken and written English communication skills.

Responsibilities

• Develop verification plans in collaboration with design and system teams to ensure first-pass silicon success.
• Implement mixed-signal testbenches in Cadence and SystemVerilog to apply stimulus and checks.
• Create automatic checks and measurements to verify DUT behavior and populate a SCM.
• Run coverage regressions to meet defined goals.
• Communicate verification status and issues to the project team.

Skills

Electronics design experience

Verilog/VHDL

English communication

Scripting (Python/C++)

Education

Bachelor's degree in Electrical/EE/EC

Master's degree in EE/related field

Tools

Cadence Virtuoso

SystemVerilog/Verilog-A/Verilog-AMS

Job description

Texas Instruments in Oulu, Finland is seeking a Design Verification Engineer to verify analog and mixed-signal ICs during the design phase. You will develop simulation test benches, automated checkers, and reports for the project team, collaborating across functions to drive defects to closure and increase DV skills with TI's CAP program.

You will work under a senior DV engineer, gain exposure to digital/analog design paths, and contribute to DV strategy and tool improvements for efficient