Lead Physical Design Engineer - Tapeout Expert

Drive Capital; København; On-site; DKK 800,000 - 1,200,000; Full time

Job summary

Normal Computing is seeking a seasoned Physical Design Engineer to own end-to-end silicon realization, from synthesis and floorplanning to timing signoff and GDSII tapeout. You’ll collaborate with RTL, architecture, and DFT teams to optimize PPA and drive successful tapeouts.

You will lead full back-end flows, improve floorplanning, P&R, CTS, STA, DRC/LVS, and post-silicon support, ensuring robust physical feasibility across advanced architectures.

Qualifications

• At least 3 tapeouts from netlist to signoff.
• Deep hands-on experience with physical design tools for floorplanning, P&R, CTS, and signoff timing closure.
• Strong problem-solving skills in STA timing bottlenecks, IR/EM issues, and DRC/LVS signoff.

Responsibilities

• Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, CTS, and P&R.
• Own static timing analysis (STA) and signoff timing closure across corners and modes.
• Drive physical optimization for power, performance and area and ensure integrity (IR/EM) and cross-talk control.
• Execute full chip/block physical signoff checks (DRC/LVS/ERC) and handoff to foundry.
• Collaborate with RTL, architecture, and DFT teams to influence early floorplanning and feasibility.

Skills

Tapeout Track Record

PD Flow Expertise

Backend Debugging

Cross-Functional Feasibility

Tools

Innovus

IC Compiler II

Tempus

PrimeTime

Pegasus

Calibre

Job description

Normal Computing is seeking a seasoned Physical Design Engineer to own end-to-end silicon realization, from synthesis and floorplanning to timing signoff and GDSII tapeout. You’ll collaborate with RTL, architecture, and DFT teams to optimize PPA and drive successful tapeouts.

You will lead full back-end flows, improve floorplanning, P&R, CTS, STA, DRC/LVS, and post-silicon support, ensuring robust physical feasibility across advanced architectures.