Digital IC Design Engineer (EP-ESE-ME-2025-225-GRAP)

jobr.pro; Genf; Hybrid; CHF 100’000 - 125’000; Vollzeit

Zusammenfassung

A leading research organization in Geneva is seeking a Digital ASIC Design Engineer to work on advanced MAPS particle-detector ASICs. The role involves designing, implementing, and verifying high-performance circuits and collaborating with a multidisciplinary team. Ideal candidates have a strong background in digital IC design, proficiency in hardware description languages, and experience in both ASIC and FPGA environments. This position offers a hybrid work model and a competitive monthly stipend of 6287 to 6911 Swiss Francs.

Leistungen

Coverage by CERN's health scheme

Membership of the CERN Pension Fund

30 days of paid leave per year

On-the-job training at CERN

Formal language courses for English and/or French

Qualifikationen

• Experience in digital IC design with a strong understanding of VLSI principles.
• Strong knowledge of digital or mixed-signal circuits in ASICs or FPGAs.
• Experience with digital simulation techniques and tools is a plus.

Aufgaben

• Conceive and optimise system-level architectures and data processing strategies.
• Design, synthesise, and implement RTL, including timing closure and place & route.
• Contribute to chip signoff through physical design checks and power integrity analysis.
• Participate in formal verification using UVM methodologies.
• Manage the full RTL-to-GDS flow and physical signoff with professional tools.

Kenntnisse

Digital IC design

VLSI principles

Hardware description languages (Verilog/SystemVerilog, VHDL)

Scripting languages (Python, TCL, Shell)

Versioning tools (Git)

Functional verification methodologies (UVM/SystemVerilog)

Spoken and written English

Commitment to learn French

Ausbildung

Master's degree in Electronics engineering or related field

PhD in Electronics engineering or related field

Jobbeschreibung

Job Description

We are looking for a digital ASIC design engineer to work on the next generation of advanced MAPS particle-detector ASICs for the CERN detector complex. You will contribute to the design, implementation, and verification of high-performance digital readout and control circuits that meet demanding targets in speed, density, power efficiency, and radiation tolerance, while collaborating closely with analog and verification specialists.

Your Responsibilities:

• Conceive and optimise system-level architectures and data processing strategies.
• Design, synthesise, and implement RTL, including timing closure and place & route of complex designs.
• Contribute to chip signoff through physical design checks (DRC, LVS, ERC) and power integrity analysis.
• Participate in formal verification using UVM methodologies.
• Manage the full RTL-to-GDS flow and physical signoff with professional EDA tools.
• Collaborate and communicate effectively within a multidisciplinary team.
• Learn and share knowledge, solve problems, and achieve results through teamwork.

Your Profile:

• Experience in digital IC design with a strong understanding of VLSI principles.
• Experience in the design and implementation of digital or mixed-signal circuits in ASICs or FPGAs.
• Additionally, experience with digital simulation techniques and tools would be an advantage.

Skills:

• Proficiency in RTL design using hardware description languages (Verilog/SystemVerilog, VHDL).
• Proficiency in scripting languages (Python, TCL, Shell) and versioning tools (Git).
• Additionally, experience with functional verification methodologies (UVM/SystemVerilog) and simulation tools would be an advantage.
• Spoken and written English, with a commitment to learn French.

Eligibility Criteria:

• You have a professional background in Electronics engineering (or a related field) and have either:
• a Master's degree with 2 to 6 years of post-graduation professional experience;
• or a PhD with no more than 3 years of post-graduation professional experience.
• You have never had a CERN fellow or graduate contract before.
• a Master's degree with 2 to 6 years of post-graduation professional experience;
• or a PhD with no more than 3 years of post-graduation professional experience.

Additional Information

• Job closing date: 06.01.2026 at 23:59 CET.
• Contract duration: 24 months, with a possible extension up to 36 months maximum.
• Job flexibility: Hybrid
• Target start date: 01-February-2026

This Position Involves:

• Work during nights, Sundays and official holidays, when required by the needs of the Organization.
• Job reference: EP-ESE-ME-2025-225-GRAP
• Field of work: Electrical or Electronics Engineering
• Benchmark job: 200050 - Electronics Engineer

What We Offer

• A monthly stipend ranging between 6287and 6911Swiss Francs per month (net of tax).
• Coverage by CERN's comprehensive health scheme (for yourself, your spouse and children), and membership of the CERN Pension Fund.
• Depending on your individual circumstances: installation grant; family, child and infant allowances; payment of travel expenses at the beginning and end of contract.
• 30 days of paid leave per year.
• On-the-job and formal training at CERN as well as in-house language courses for English and/or French.

About Us

At CERN, the European Organization for Nuclear Research, physicists and engineers are probing the fundamental structure of the universe. Using the world's largest and most complex scientific instruments, they study the basic constituents of matter - fundamental particles that are made to collide together at close to the speed of light. The process gives physicists clues about how particles interact, and provides insights into the fundamental laws of nature. Find out more on http://home.cern.

We are on a Quest. A Journey into discovery like no other. Bring your expertise to our unique work and develop your knowledge and skills at pace. Join world-class subject matter experts on unique projects, in a Quest for greater knowledge and deeper understanding.

Begin your CERN Quest. Take Part!

Diversity has been an integral part of CERN's mission since its foundation and is an established value of the Organization. Employing a diverse workforce is central to our success.