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CERN in Geneva invites a digital ASIC design engineer to work on the next generation of MAPS particle-detector ASICs for the CERN detector complex. You will contribute to the design, implementation, and verification of high-performance digital readout and control circuits that meet demanding targets in speed, density, power, and radiation tolerance.
You will collaborate closely with analog and verification specialists and meet eligibility criteria: a master’s degree with 2–6 years since
Datum: 21 april, 2026 Tid: 11:59
Placering: CERN
We are looking for a digital ASIC design engineer to work on the next generation of advanced MAPS particle-detector ASICs for the CERN detector complex. You will contribute to the design, implementation, and verification of high-performance digital readout and control circuits that meet demanding targets in speed, density, power efficiency, and radiation tolerance, while collaborating closely with analog and verification specialists.