Validation Engineer - HCLTech

Bilinguallink; North Vancouver; On-site; CAD 110,000 - 150,000; Full time

Job summary

Bilinguallink in Vancouver area seeks an experienced SoC Validation Engineer to drive end-to-end validation of complex SoC designs across pre-silicon and post-silicon phases. The role focuses on IP subsystems such as Clock, Reset, Ethernet, and I/O controllers with test strategies, validation plans, and root-cause analysis from simulation to production.

The ideal candidate will develop and execute robust validation plans, verify clock domains, reset behavior, and data paths, and collaborate with

Qualifications

• Bachelor's degree in EE/related field or higher required.
• 4–10+ years of SoC validation experience (pre- and/or post-silicon).
• Strong understanding of SoC IP integration and validation methodologies.

Responsibilities

• Develop and execute validation plans for pre- and post-silicon IP subsystems.
• Verify clocks, resets, Ethernet, and I/O interfaces and ensure functional correctness.
• Perform CDC checks, power-on reset behavior, and integration verification.
• Debug silicon issues using analysis tools and collaborate with design/firmware teams.
• Develop automated test frameworks and contribute to regression tests.

Skills

SoC validation

Test strategy development

CDC verification

RTL debugging

Emulation/FPGA prototyping

Test automation

Education

Bachelor's degree in Electrical Engineering

Tools

Python

Perl

Tcl

JTAG

Emulation platforms (Palladium/Veloce/Protium)

Job description

Job Title

SoC Validation Engineer — Pre-Silicon & Post-Silicon

Summary

We are looking for an experienced SoC Validation Engineer to drive end-to-end validation of complex System-on-Chip (SoC) designs across both pre-silicon and post-silicon phases. The ideal candidate brings deep domain expertise in SoC IP subsystems — including Clock, Reset, Ethernet, I/O controllers, and related infrastructure IPs — with proven ability to develop test strategies, execute validation plans, and root-cause failures from simulation through first silicon and production.

Key Responsibilities

• Pre-Silicon Validation
  • Develop comprehensive verification and validation plans for SoC-level IP subsystems including Clock Generation/Distribution (PLLs, clock muxes, dividers), Reset Architecture, Ethernet MAC/PHY, and I/O interfaces (GPIO, I2C, SPI, UART, JTAG)
  • Create and execute directed and constrained-random tests targeting IP integration, connectivity, and functional correctness at the SoC level
  • Verify clock domain crossings (CDC), reset sequencing, and power-on reset (POR) behavior
  • Validate Ethernet data path integrity, link negotiation, and MAC-to-PHY (MII/RGMII/SGMII) interfaces
  • Perform functional coverage analysis and drive coverage closure across IP blocks
  • Collaborate with design and architecture teams on RTL debug, assertions, and specification reviews
  • Execute validation on emulation/FPGA prototyping platforms (Palladium, Veloce, Protium) for early software/firmware integration
• Post-Silicon Validation
  • Bring up and validate SoC IPs on first silicon and platform boards
  • Develop and execute post-silicon test plans covering:
    • Clock: PLL lock times, frequency accuracy, jitter characterization, clock switching, glitch-free mux transitions
    • Reset: Reset assertion/de-assertion sequencing, warm/cold reset flows, watchdog timer resets, brown-out detection
    • Ethernet: Link bring-up, auto-negotiation, packet integrity (CRC/FCS), throughput/latency, loopback testing, PTP/IEEE 1588 timestamping
    • I/O: Pin mux configuration, drive strength, voltage levels, protocol compliance (I2C/SPI/UART timing), interrupt routing
  • Debug silicon failures using oscilloscopes, logic analyzers, protocol analyzers, JTAG/DFx, and embedded trace tools
  • Perform root-cause analysis of post-silicon bugs and drive resolution with design and firmware teams
  • Characterize IP performance under varying voltage, frequency, and temperature (VFT) conditions
  • Develop and maintain automated test frameworks for regression and production testing
  • Collaborate with platform, firmware, BSP, and driver teams on system-level integration and debug
• General
  • Author and maintain validation documentation: test plans, debug reports, coverage metrics, and known-issue databases
  • Develop Python/Perl/Tcl scripts for test automation, log parsing, and result analysis
  • Participate in silicon bring-up triage, failure analysis, and bug review meetings
  • Mentor junior engineers and drive process improvements in validation methodology
  • Interface with IP vendors for third‑party IP integration, compliance, and issue resolution

Required Qualifications

• Education: B.S./M.S./Ph.D. in Electrical Engineering, Computer Engineering, or related field
• Experience: 4–10+ years in SoC validation (pre‑silicon and/or post‑silicon)
• Deep understanding of SoC architecture and IP integration concepts

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