Senior System Safety Engineer

AeroVect; Vancouver; On-site; CAD 120,000 - 180,000; Full time

Job summary

AeroVect is hiring a Senior Safety Engineer to lead hardware safety analyses and be a core contributor to safety cases for autonomous ground handling systems.

You will derive safety requirements, perform hazard assessments, and work with cross-functional teams to ensure safety is integrated across software, hardware, and test activities. Experience in automotive or aerospace safety frameworks is highly valued.

Qualifications

• 5+ years of hands-on safety engineering experience in autonomous systems.
• Experience with ISO 26262, DO-178C/DO-254, and IEC 61508.
• Background in hardware safety engineering, EE reliability, or failure rate modeling.
• Experience with autonomous driving systems or mobile robotics.
• BS/MS in CS/EE/Systems/Robotics or related field.

Responsibilities

• Perform hardware safety analyses incl. FMEDA and PMHF.
• Calculate hardware failure rates using standard methods (SN 29500, IEC 61709).
• Evaluate drive-by-wire compute hardware and sensors for faults.
• Derive Hardware Safety Requirements for redundant architectures.

Skills

System safety

Requirements derivation

Cross-functional

Safety case

FMEDA

Hardware safety

ISO 26262

DO-178C/DO-254

SPFM/LFM

Failure rate modeling

Education

Bachelor's or master's in a relevant field

Job description

Who We Are

AeroVect is transforming ground handling with autonomy, redefining how airlines and ground service providers around the globe run day-to-day operations. We are a Series A company backed by top-tier venture capital investors in aviation and autonomous driving. Our customers include some of the world’s largest airlines and ground handling providers. For more information, visit www.aerovect.com.

Working under the close guidance and supervision of the Head of Safety, the Senior Safety Engineer will execute core safety lifecycle tasks across AeroVect's software and hardware platforms:

• System Safety Analysis: Perform hazard identification and risk assessments (HARA, FMEA, FTA, STPA) on the autonomous system architecture and vehicle operation concepts.
• Requirements Derivation: Derive, specify, and trace functional and technical safety requirements (FSRs / TSRs) for both supervised autonomy (safety driver present) and SDO unsupervised autonomy (driverless).
• Cross-Functional Execution: Collaborate directly with systems, software, robotics, hardware, and test teams to ensure safety requirements are integrated, testable, and verified.
• Safety Case Support: Assist in building safety case artifacts and verification evidence required for airport commercial deployment.

You Will

• Perform Quantitative Hardware Safety Analyses, including FMEDA, hardware diagnostic coverage analysis, and Probabilistic Metric for random Hardware Failures (PMHF).
• Calculate hardware component and system failure rates using standard methodologies (SN 29500, IEC 61709, MIL-HDBK-217F, Telcordia SR-332).
• Evaluate drive-by-wire compute hardware, sensor suites (Lidar, Radar, Camera), actuator interfaces, and power distribution systems for single-point and latent faults.
• Derive Hardware Safety Requirements (HSRs) for redundant architectures and fail-operational compute nodes.

You Have

• 5+ years of hands-on safety engineering experience in autonomous vehicles, automotive (ISO 26262), aerospace (DO-178C/DO-254), or industrial safety (IEC 61508).
• 5+ years in hardware safety engineering, EE reliability, or failure rate modeling for automotive, aerospace, or industrial robotics.
• Prior background working with autonomous driving systems or mobile robotics.
• Proven ability to work under the technical mentorship of a Principal Safety Engineer in a high-velocity agile engineering team.
• B.S. or M.S. in Computer Science, Electrical Engineering, Systems Engineering, Robotics, or a related discipline.
• Proven mastery of FIT rate modeling, component failure rate calculation methods (SN 29500, IEC 61709, MIL-HDBK-217), and FMEDA workflows.
• ISO 26262-5 Mastery: Deep knowledge of hardware architectural metrics (SPFM, LFM) and hardware diagnostic strategies.