Senior Silicon Engineer

Qorsa Corp; Southwestern Ontario; On-site; CAD 120,000 - 180,000; Full time

Benefits offered by this job

Stock options

Dental care

Extended health care

Vision care

On-site parking

Job summary

Qorsa Corp is seeking a senior silicon design engineer to lead hardware design for a cryptography-focused chip program. You will own the digital design flow from RTL through tape-out, manage the design process, and collaborate closely with security and cryptographic teams to ensure hardware/software interface integrity.

The role demands deep digital ASIC expertise, hands-on leadership, and the ability to navigate non-standard flows beyond textbook answers.

Qualifications

• Must have track record in digital ASIC design from RTL through physical implementation.
• Experience taking at least one chip through tape-out.
• Strong leadership and mentoring abilities.
• Excellent cross‑disciplinary communication with software, security, and cryptography teams.

Responsibilities

• Own the full digital design flow from RTL to tape-out and GDS‑II handoff.
• Build and manage hardware engineering processes; mentor engineers and scale the team.
• Collaborate with security and cryptographic leads on hardware/software interfaces and certification constraints.
• Drive design-for-manufacturing across process nodes with foundries (DRC/DFM/tech migration).
• Maintain verification environment: simulation, formal verification, and electrical verification.
• Contribute to certification strategy and ensure documentation and traceability evidence.

Skills

Digital ASIC design

RTL to tape‑out

Technical leadership

Hands-on design

Engineering mentorship

Effective communication

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

Synopsys

Siemens EDA

Job description

About Qorsa

Qorsa is a Canadian post-quantum cryptography and cybersecurity company building CasQade - a crypto-agile security platform protecting sovereign government, defence, financial, and critical-infrastructure networks against current and emerging cryptographic threats. We are headquartered in Waterloo, Ontario, with a European subsidiary in The Hague, Netherlands. Our work spans post-quantum cryptography, explainable AI, AI-driven threat intelligence, cryptographic agility, hardware security, and distributed systems, with active engagements across Canadian defence, NATO, and allied partner organizations.

The Role

We are hiring a senior silicon design engineer to be part of the hardware design of a chip program at the core of our platform. This is a hands-on technical leadership role. You will own the design from RTL through physical implementation and tape-out, build and manage the hardware engineering processes, and partner closely with our security and cryptographic engineering leads on the interface between the software stack and the silicon that executes it.

This is a senior role with significant technical influence and close collaboration across our engineering and research teams.

This is frontier work. The design does not follow a conventional template, and much of the value you bring will be judgement in the places where the standard flow and off-the-shelf tooling stop being sufficient. We need someone who understands digital design from first principles - not just how to run the flow, but why it works - and who is energized rather than deterred by problems that don't have a textbook answer.

Responsibilities

• Own the full digital design flow - RTL design, synthesis, place-and-route, timing and physical verification - through to tape-out and GDS-II delivery.
• Build and manage the hardware engineering process: scope and assign work, review designs, maintain design integrity as the team scales, and mentor engineers. Grow the team's capability over time.
• Partner with the hardware security and cryptographic engineering leads on the hardware-software interface and certification-driven design constraints.
• Drive design-for-manufacturing across target process nodes, working with foundry partners on DRC, DFM, and technology migration.
• Stand up and maintain the verification environment - simulation, formal verification, design-rule checking, and electrical verification.
• Own the tape-out process end to end, from design freeze through GDS-II handoff to the foundry.
• Contribute to certification strategy by ensuring the design meets the documentation, traceability, and evidence requirements of target frameworks.
• Build and maintain the EDA tooling and design flow for the hardware team.

What We're Looking For

• A track record in digital ASIC design from RTL through physical implementation, with at least one chip taken through tape-out. You know what that process demands end to end.
• Deep command of digital design fundamentals — you understand the methodology well enough to work confidently where it doesn't directly apply, and you don't rely on tool defaults to tell you what's correct.
• Fluency with industry-standard design flows and EDA tools (Cadence, Synopsys, Siemens EDA, or equivalent).
• Experience with digital verification — simulation, formal methods, or both.
• Design-for-manufacturing experience at process nodes below and above 90nm, including applying design rules and DRC for a recognized foundry (GlobalFoundries, TSMC, Samsung, Intel, STMicroelectronics, or equivalent).
• Experience with timing and electrical verification — static timing analysis, LVS, ERC, and parasitic extraction.
• Strong leadership and people-management ability. You can build and grow a team, decompose a complex design into clear, well-scoped work packages, and hold the whole architecture in your head while doing it.
• Excellent communication skills and genuine comfort working across disciplines — you will be in constant contact with software, security, and cryptography engineers, and you need to translate fluently between hardware realities and theirs.
• The instincts of a player-coach: doing hands-on design alongside the team, not directing from a distance.

Strong Assets

• Experience with side-channel-resistant design.
• Comfort with custom or non-standard design flows, where off-the-shelf EDA assumptions don't fully hold.
• Experience migrating a design from one process node to a smaller node.
• Experience with resolution-enhancement technology (RET) and/or optical proximity correction (OPC), including flows and optimization.
• Familiarity with mask-making processes and the foundry interface.
• Mixed-signal or analog design experience.
• FPGA prototyping as a path to ASIC.
• Familiarity with cryptographic hardware design or hardware security modules.
• Experience building and supporting small engineering teams.
• Eligibility for Government of Canada security clearance (Secret level).

Compensation

We compensate exceptionally well - a strong base salary plus meaningful stock options in a rapidly growing company.

Benefits

• Dental care
• Extended health care
• Vision care
• On-site parking

Work Location:

In person, Waterloo, Ontario.