Principal ASIC Verification Engineer

Nokia; Ottawa; On-site; CAD 100,000 - 130,000; Full time

Job summary

A leading technology firm in Ottawa is seeking an experienced ASIC Verification Engineer. Responsibilities include verifying complex SoCs and collaborating with various engineering teams to deliver innovative solutions. The ideal candidate has over 8 years of experience in ASIC verification, is fluent in System Verilog and Python, and possesses excellent problem-solving skills.

Qualifications

• Minimum 8+ years of relevant experience in the ASIC verification field.
• Experience developing and implementing test plans for complex ASICs.
• Fluent in System Verilog and Python.

Responsibilities

• Develop and verify cutting-edge SoCs using the latest technology.
• Create and implement test plans based on functional and standard requirements.
• Cooperate with engineers to solve technical issues.

Skills

ASIC verification

System Verilog

Python

UVM methodology

Problem solving

Communication

Education

Bachelor's degree in Computer Science or Electrical Engineering

Master's degree

Tools

Code coverage tools

Formal verification tools

Job description

We are seeking an ASIC Verification Engineer with a solid ASIC/FPGA verification test strategy & development and debugging skills. The Network Infrastructure group is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise.

Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, we’ve united two industry leaders to create an optical networking powerhouse—combining cutting-edge technology with proven leadership to redefine the future of connectivity.

Qualifications

• Masters degree desired, Bachelor's degree in CS/EE is required.
• Minimum 8+ years of relevant experience in the ASIC verification field.
• Should have worked on developing/implementing test plans at the block or sub-chip levels for complex ASICs.
• Fluent in System Verilog and scripting languages such as Python.
• Must have intimate knowledge of UVM methodology.
• Knowledgeable about assertions and functional coverage Experience with code coverage and formal verification tools; familiarity with evolving verification methodologies.
• Strong problem solving skills.
• Very good communication skills and ability and desire to work in a geographically diverse team environment.
• Will be responsible for the definition, development, and execution of self-checking tests for complex digital ASICs.
• Knowledge of DSP and/or FEC will be desirable.

Responsibilities

• Working as independent contributor in development and verification of the world leading SoCs based on latest technology ASICs and FPGAs
• Working on System Verilog/UVM-based protocol/traffic generators/checkers
• Working on test plan based on functional requirements as well as applicable standards requirements
• Working with experts of different areas to ensure the most competitive solutions
• Cooperating with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues
• Supporting HW/SW bring-up and debug
• Work as an independent contributor or lead a team to deliver defined tasks.