Principal Analog Mixed-Signal Design Engineer

Astera Labs; Toronto; On-site; CAD 233,000 - 297,000; Full time

Benefits offered by this job

Discretionary bonus

Job summary

Astera Labs seeks a Principal Analog Mixed-Signal Design Engineer to architect and implement high-performance analog blocks for SerDes, PHY, and high-speed I/O. You will own designs from concept through silicon bring-up, setting the bar for the analog team and mentoring colleagues.

The role demands 8+ years in analog/mixed-signal IC design, strong SI knowledge, and hands-on proficiency with Cadence tools. You will work in a high-impact environment focused on AI connectivity in data centers.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 8+ years of analog/mixed-signal IC design experience.
• Proven track record designing high-speed analog circuits (PLLs, SerDes, data converters, references, regulators) in CMOS/FinFET nodes.
• Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.
• Proficiency with Cadence Virtuoso and simulation tools; layout/parasitic-aware design.

Responsibilities

• Architect and design high-speed analog/mixed-signal circuits for SerDes, PHY, and high-speed I/O.
• Lead design from concept through silicon bring-up; supervise layout and verification across PVT corners.
• Mentor engineers and set design methodologies; collaborate with digital, physical design, and systems teams.
• Define and execute test plans to correlate silicon performance with targets.
• Lead silicon bring-up, characterization, debugging, and design-for-test activities.

Skills

Analog design

Mixed-signal design

High-speed I/O

PLL design

SerDes basics

Cadence Virtuoso

Physical-layer

Education

MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Job description

Principal Analog Mixed-Signal Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is redefining the connectivity that powers rack-scale AI infrastructure, and analog design is at the heart of it. As a Principal Analog Mixed Signal Design Engineer, you will architect and design the high-performance analog and mixed-signal circuits that anchor our SerDes, PHY, and high-speed I/O — the silicon building blocks that move data at the speed AI demands. Your work directly shapes the performance, power, and reliability of products deployed in the world's most advanced data centers.

This is a high-impact, hands-on role at a hyper-growth company purpose-built for AI connectivity. You will own designs from concept through silicon bring-up, set the technical bar for the analog team, and mentor engineers as we scale. If you want your circuits to enable the next generation of AI compute, this is where that happens.

Key Responsibilities

Analog & Mixed-Signal Design

Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, high-speed SerDes building blocks, ADCs/DACs, and clocking.

Drive circuit design from specification and architecture through schematic, layout supervision, and verification across PVT corners.

Develop robust designs in advanced FinFET process nodes with attention to power, area, and performance trade-offs.

Lead silicon bring-up, characterization, and debug, partnering with validation and product engineering to root-cause and resolve issues.

Define and execute test plans to correlate silicon performance against design targets.

Technical Leadership

Set analog design methodology, review standards, and best practices across the team.

Partner cross-functionally with digital, physical design, systems, and architecture teams to deliver full-chip solutions.

Mentor and guide junior engineers, elevating the technical capability of the analog organization.

Basic Qualifications

MS or PhD in Electrical Engineering or a related field.

8+ years of experience in analog and mixed-signal integrated circuit design.

Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes.

Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O.

Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills.

Preferred Qualifications

Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing.

Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures.

Familiarity with silicon debug, ATE test development, and design-for-test techniques.

Experience mentoring engineers and leading technical design reviews.

Excellent communication skills and a collaborative, ownership-driven mindset.

Salary range is $165,000 to $210,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Voluntary Self‑Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Astera Labs’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection. As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.