IP Silicon Validation Engineer

Advanced Micro Devices, Inc; Markham; On-site; CAD 90,000 - 130,000; Full time

Job summary

Advanced Micro Devices, Inc. (AMD) is seeking an IP Validation Design Engineer to drive validation, debug, and quality for AMD IPs across APU/CPU/Compute/SOC programs.

You will define functional test plans, coordinate cross-functional teams, and push innovations in validation methods and automation. Ideal candidates have strong digital design/verification experience, ASIC debugging skills, and the ability to work across sites/time zones.

Qualifications

• Experience in digital logic design/verification/post-silicon validation.
• Strong ASIC debug techniques and methodologies.

Responsibilities

• Define, document, execute and report validation plans for AMD IPs.
• Drive technical innovation in IP validation, tools, and automation.
• Debug IP issues across pre-silicon, bring-up and system validation phases.
• Collaborate with DV, Diagnostics, Emulation and other teams to ensure readiness for silicon.

Skills

Digital design

Verification

Pre-silicon validation

Communication

Scripting (Python/Ruby)

Education

Bachelor's or Master's in EE/CS

Tools

Oscilloscopes

Logic analyzers

Protocol analyzers

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE:

The AMD NBIO Team is on the lookout for a dynamic, upbeat IP Validation Design Engineer to join our growing team. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and validation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You are a self-starter with strong analytical and problem-solving skills and are willing to learn and ready to independently drive tasks to completion.

KEY RESPONSIBILITIES:

As an IP Validation Design Engineer, you will drive the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs.

• Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s.


• Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.


• Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs.


• Engaging on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features.


• Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives.


• Developing knowledge of system architecture/debug and other internal IP’s.


• Supporting issues on customer platforms as requested by customer support teams.

PREFERRED EXPERIENCE:

• Experience in digital logic design/verification/post-silicon validation.


• Extensive experience with ASIC debug techniques and methodologies.


• Knowledge of physical and protocol levels of common high-speed interfaces such as PCIe/CXL/UALINK is an asset


• Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization.


• Strong scripting skills (eg. Ruby, Python).


• Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.


• In-depth knowledge of PC architectures/PCIe protocol is an asset.


• Must have excellent written and verbal communication skills.


• Must excel in a dynamic team working environment.


• Leadership and mentoring skills a definite asset.


• Must be a self-starter and be able to independently drive tasks to completion.

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree majoring in EE, CS or related field

LOCATION: Markham, Vancouver

#LI-TB2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.