HLS Design Engineer, WIFI Physical Layer

Qualcomm; Vancouver; On-site; CAD 80,000 - 110,000; Full time

Job summary

A leading technology innovator is seeking an ASIC Engineer in Vancouver to design and validate high-performance ASIC products. Responsibilities include designing advanced WiFi functionalities, developing models, and ensuring quality checks. Candidates should have a degree in engineering and significant ASIC experience. Qualcomm offers a dynamic work environment with a commitment to innovation.

Qualifications

• 4+ years of ASIC design, verification or related work experience.
• Experience working with algorithms and systems modeling.
• Familiarity with verification methods.

Responsibilities

• Design and test advanced WiFi functionalities.
• Convert models into ASIC hardware using SystemC/C++.
• Develop unit-level and integrated-level test-bench.

Skills

ASIC design

C/C++ development

SystemC

design verification

team collaboration

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

High-Level Synthesis (HLS)

EDA tools

Job description

Company: Qualcomm Canada ULC

Job Area: Engineering Group, ASICS Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next‑generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world‑class products. Qualcomm Engineers collaborate with cross‑functional groups to determine product execution path.

Responsibilities

• Working with the WiFi algorithm and systems team to design and test advanced WiFi functionalities such as OFDM and OFDMA modulators and demodulators, transmit beamforming, timing and synchronization, RF impairment correction, and adaptive filters.
• Working with the algorithms/systems/modeling team to obtain a fixed‑point/finite‑precision C/C++ model that is realizable in optimized ASIC hardware.
• Converting the finite‑precision models into ASIC hardware using SystemC/C++ for HLS (High‑Level Synthesis) as the primary hardware description language that meets area and power targets.
• Working with the verification engineers to develop unit‑level and integrated‑level test‑benches.
• Debugging the designs in stand‑alone and integrated with the system.
• Synthesis and gate‑level timing tasks related to the designed module and assist with verification and timing of the entire chip.
• Design quality checks such as lint, CDC, and low‑power rule checks.
• RTL‑level and gate‑level vector‑based power analysis.
• Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
• Creates advanced architectures, circuit specifications, logic designs, and/or system simulations based on system‑level requirements.
• Collaborates across functional teams to develop and execute an implementation strategy that meets system requirements and customer needs.
• Evaluates all aspects of complex process flow from high‑level design to synthesis, place and route, timing and power use, and verification for custom circuit design/layout flow.
• Utilizes tools/applications to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC packages.
• Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications

• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• 6+ years of ASIC design, verification, validation, integration, or related work experience; 2+ years of experience with HLS using SystemC or C++; 2+ years of experience with scripting tools and programming languages.
• 2+ years of experience with design verification methods.
• 1+ year of work experience in a role requiring interaction with senior leadership (e.g., director level and above).

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑[e-mail] or call Qualcomm's toll‑free number. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able to participate in the hiring process.

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