Display ASIC Design Verification Engineer

Qualcomm; Markham; On-site; CAD 80,000 - 120,000; Full time

Job summary

Join Qualcomm's display design team as an ASIC Design Verification Engineer, contributing to the next generation of Display Processors. This role involves collaboration within a multi-disciplinary team, focusing on design verification, simulation, and documentation for high-performance hardware systems.

Qualifications

• Bachelor's degree in relevant field.
• Strong C/C++ background and debugging skills required.
• Knowledge in digital circuit design and verification methodologies.

Responsibilities

• Contribute to verification during the design phase of ASICs.
• Work with the design team to define verification requirements.
• Participate in test plan development and execute verification.

Skills

Analytical skills

Debugging skills

C/C++

Object Oriented Programming (OOP)

SystemVerilog

Verilog

Digital circuits knowledge

Perl

Python

TCL

Strong communication

Detail-oriented

Education

Bachelor's degree in Science, Engineering, or related field

Job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Join the display design team as an ASIC Design Verification engineer where you will be part of a highly experienced multi-disciplinary and multi-site team that values collaboration, creativity, innovation and productivity. In this role you will help build next generation Display Processors that are key to delivering vivid and stunning visual experiences in the mobile, compute, automotive, and IoT markets. The candidate will work with industry leading edge HW Design Verification methodology and processes and provide expertise for next generation initiatives.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field.

Required Skills/Experience:

• Strong analytical and debugging skills
• Good working experience with C/C++
• Strong knowledge of Object Oriented Programming (OOP) concepts
• Hardware verification languages (HVL): SystemVerilog testbench (UVM), and/or SystemC
• Hardware description languages (HDL): Verilog and SystemVerilog
• Knowledgeable in one or more of the following disciplines is preferred: Display (Pixel processing/composition/compression, MIPI DSI, DisplayPort, HDMI etc.), Bus/interconnect (AHB, AXI)
• Strong knowledge of digital circuits and event-driven simulators
• Knowledgeable with Perl, Python, TCL, tcsh, and GNU Make
• Strong communication skills (written and verbal) to convey complex information to peers.
• Detailed oriented and be able to plan and prioritize tasks effectively.

Principal Duties & Responsibilities:

• Contribute to feature, core and sub-system verification during the design and development phase of next generation ASICs through C/RTL and Gate Level simulations.
• Work closely with the design team to define verification requirements to ensure functional, performance and power correctness.
• Participate in test plan development, execution and verification closure.
• Contribute to creating/maintaining test benches, assertions, and functional coverage models.
• Contribute to implementing flows to automate development processes.
• Participate in debug activities throughout the development cycle.
• Applies ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
• Creates architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
• Collaborates across teams (e.g., software architecture, hardware architecture) to develop and execute an implementation strategy that meets system requirements and customer needs.
• Evaluates all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
• Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.
• Writes detailed technical documentation for EDA/IP/ASIC projects.

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