Digital Design Verification Engineering Internship (16-Month Co-op)

Synopsys Inc; Mississauga; Hybrid; CAD 22,000 - 28,000; Full time

Job summary

Synopsys Inc. invites you to join as a Digital Design Verification Engineering Intern in Mississauga, Ontario. The 16-month program runs in a hybrid model, starting May 2027, with in-office and remote collaboration.

You’ll verify Backplane Ethernet, PCIe, SATA, USB 2/3, and MIPI CPHY/DPHY SERDES designs and work on real customer projects with global teams. You’ll gain hands-on experience with SystemVerilog, UVM, constrained random testbenches, coverage, assertions, and debugging while

Qualifications

• Pursuing a Bachelor's degree in Computer Engineering or Electrical Engineering with co-op/internship experience.
• Strong interest in digital design and verification with related coursework.
• Proficiency in Perl or Python.
• Knowledge of Verilog and/or SystemVerilog.
• Basic Unix/Linux shell proficiency.

Responsibilities

• Defining and tracking Verification Testplans to ensure coverage of design functionality.
• Designing and writing constrained-random SystemVerilog testbenches using UVM and directed testbenches for ATE/Customer applications.
• Creating and examining Functional Coverage and writing SystemVerilog assertions to validate design behavior.
• Debugging RTL and gate-level simulation failures, performing Code Coverage Analysis and Closure, and tracking bugs using Jira.
• Leveraging AI to enhance verification tasks and workflows, collaborating with design engineers in Portugal and verification teams in Cairo.

Skills

Digital design

SystemVerilog

Verilog

Python

Unix/Linux

Communication

Collaboration

Education

Bachelor's degree pursuit in Computer or Electrical Engineering

Tools

Jira

UVM

Job description

We Are:

Drive technology innovations that shape the way we live and connect. Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

Internship Experience:

At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide - and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Mission Statement:

Our mission is to fuel today's innovations and spark tomorrow's creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive - both at work and beyond.

What You'll Be Doing:

As a Digital Design Verification Engineering Intern, you'll be involved in verifying current and next-generation Backplane Ethernet, PCIe, SATA, USB 2/3, and MIPI CPHY/DPHY SERDES products. This is a critical step in the product development process, ensuring designs comply with Protocol Standards and System Requirements before they become chips. You'll work on real customer projects alongside global teams, gaining hands-on experience that will position you as an entry-level engineer by the end of your internship.

Your day-to-day responsibilities will include:

• Defining and tracking Verification Testplans to ensure comprehensive coverage of design functionality
• Designing and writing constrained-random SystemVerilog testbenches using UVM (Universal Verification Methodology) and directed testbenches for ATE/Customer applications
• Creating and examining Functional Coverage and writing SystemVerilog assertions to validate design behavior
• Debugging RTL and gate-level simulation failures, performing Code Coverage Analysis and Closure, and tracking bugs using tools such as Jira
• Leveraging AI to enhance verification tasks and workflows, gaining hands-on experience with cutting-edge technologies while collaborating with design engineers in Portugal and verification teams in Cairo

What You'll Need:

• Currently pursuing a Bachelor's degree in Computer Engineering, Electrical Engineering, or a related discipline with previous co-op or internship experience
• Strong interest in digital design and verification, supported by relevant coursework
• Proficiency in scripting languages like Perl or Python
• Comprehensive knowledge of Verilog and/or SystemVerilog language
• Basic proficiency with Unix/Linux shell environments
• Confident communication and initiative - you're comfortable asking questions, connecting with team members across different time zones and locations, and proactively seeking guidance when encountering challenges
• Independent and resourceful - we're looking for interns who take ownership of their work, remove their own blockers, and actively pursue learning and growth opportunities

Key Program Facts:

Program Length: 16 months

Location: Mississauga, Ontario, Canada

Working Model: Hybrid (combination of remote work and in-office collaboration at our Mississauga office)

Full-Time/Part-Time: Full-Time

Start Date: May 2027

Equal Opportunity Statement:

Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us at [e-mail].