ASIC Verification Engineer

NETINT Technologies, Inc.; Markham; On-site; CAD 80,000 - 110,000; Full time

Job summary

A tech startup in Canada is seeking an ASIC verification engineer. In this role, you will verify high-performance SoC designs and collaborate with design engineers. Candidates should have a degree in Electrical or Computer Engineering and experience in verification methodologies. Proficiency in Perl and Python is a must. The position offers opportunities to work on advanced technology and be part of a dynamic team.

Qualifications

• Experience in verification using random stimulus and functional coverage.
• Hands-on experience in Perl and Python is required.
• Some knowledge of RTL coding (Verilog/VHDL), simulation, and synthesis.

Responsibilities

• Responsible for verification of the ASIC design and architecture.
• Work with designers to integrate IP Cores.
• Create functional coverage points and review results.

Skills

Verilog

System Verilog

Python

Perl

Functional coverage and assertion-based verification

Education

MS or BS in Electrical Engineering or Computer Engineering/Science

Tools

Design and verification tools

Job description

About NETINT Technologies

NETINT Technologies is a pioneer of computational storage and video processing SoC solutions for cloud and edge computing. Its Codensity portfolio enables enterprise, cloud data centers, and content providers to deploy high-performance applications that they can scale without limit while minimizing their data storage and video processing costs. NETINT, founded by an experienced team of storage SoC veterans, is a Canadian venture-funded startup with R&D facilities in Vancouver, Toronto, and Shanghai, China. For more information, visit www.netint.ca.

Job Scope

As an ASIC verification engineer, you will be part of a team to verify high-performance SoC designed by NETINT Technologies. You will work closely with ASIC design and verification engineers to verify SOC function features, close function & code coverage holes.

Responsibilities

• Responsible for verification of the ASIC design, architecture, golden models using advanced verification methodologies such as UVM. Write block & top-level tests and debugging fail tests.
• Work with designers to integrate our IP Cores
• Planning and reviewing test plans
• Creating functional coverage points
• Reviewing verification results and metrics and driving the verification convergence towards tape-out
• Run regression

Qualifications

• MS or BS in Electrical Engineering or Computer Engineering/Science
• Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
• Experience with design and verification tools
• Hands on experience in Perl and Python.
• Some Knowledge of RTL coding (Verilog/VHDL), simulation, synthesis, etc.
• Good oral and written skills for communication and documentation

Desirable Skills/Experiences

• Verilog, System Verilog
• Python & Perl programming
• Fast learner

We thank you for your interest, however, only candidates selected for an interview will be contacted.

To apply, please fill out the application form and include a copy of your transcript in your application.

Acknowledgment and Agreement

NETINT Technologies Inc. is an equal opportunity employer and strives to ensure that its hiring process meets the needs of all persons with disabilities. As such, NETINT will provide reasonable accommodation for any applicant, as requested during the hiring process.