ASIC Networking IP Verification Engineer

TekWissen LLC; Gatineau; Hybrid; CAD 80,000 - 100,000; Full time

Job summary

A global workforce management provider is seeking an experienced ASIC Networking IP Verification Engineer for a hybrid role in Gatineau. This position requires expertise in UVM methodology, networking protocols, and Synopsys tools. Ideal candidates should possess strong debugging skills, programming knowledge in System Verilog, C, and Python, and at least 5 years of verification experience. The opportunity supports workforce diversity and promotes an inclusive work environment.

Qualifications

• Minimum 5 years of experience as a Digital ASIC/FPGA Verification engineer.
• Hands-on experience with UVM methodology developing test bench components.
• Experience integrating 3rd party VIP.

Responsibilities

• Develop test sequences and functional coverage.
• Debugging and analyzing results.
• Work independently with minimum supervision.

Skills

UVM hands on experience

Networking protocol knowledge

Synopsys tools mastery

Programming languages

Excellent debugging skills

Excellent communication skills

Education

BSc in Electrical and Computer Engineering

Job description

Overview

TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions to our clients worldwide. This client is an American multinational semiconductor company based in Santa Clara, California that develops computer processors and related technologies for business and consumer markets. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.

Job Title

ASIC Networking IP Verification Engineer

Work Location

Ottawa, ON

Duration

12 Months

Work Type

Temporary Assignment

Job Type

Hybrid

Job Description

Top Must Have Skills:

• UVM hands on experience ( proven record of TB components, test sequences, functional coverage development)
• Networking protocol knowledge ( Ethernet, PCIe, AMBA AX4)
• Synopsys tools mastery ( Verdi, VCS, DVE)
• Programming languages (System Verilog, C, Python)
• ASIC verification experience
• Digital ASIC/FPGA Verification engineer with at least 5 years of experience and BSc in Electrical and Computer Engineering
• Experience in front-end ASIC verification flows (previous experience with the flows is preferred)
• Minimum 3 years hands on experience with UVM methodology developing test bench components and test sequences
• Experience integrating 3rd party VIP
• Experience writing functional coverage, analyzing results and driving towards 100% FCOV metrics
• Excellent debugging skills
• Capable to work independently with minimum supervision
• Excellent communication skills

TekWissen Group is an equal opportunity employer supporting workforce diversity.