Packaging Engineer I Semiconductors

Capgemini Engineering; Diegem; Sur place; EUR 50 000 - 75 000; Plein temps

Résumé du poste

Capgemini Engineering is seeking a Packaging Engineer in Diegem, Belgium. The position involves designing and optimizing IC packages for semiconductor applications, requiring an MSc in Electronics Engineering and a minimum of 5 years’ experience in IC package design and analysis. Ideal candidates will have hands-on experience with Cadence tools and proficiency in Ansys simulation tools. Strong communication skills in English are necessary to effectively work with clients and suppliers.

Qualifications

• Minimum of 5 years of experience in IC package design and SI/PI analysis.
• Hands-on experience with Cadence layout tools for package and backend silicon design.
• Proficiency in Ansys simulation tools for electrical and electromagnetic performance analysis.
• Strong knowledge of packaging technologies and the full IC package design lifecycle.

Responsabilités

• Designing and optimising IC packages for semiconductor applications.
• Selecting and designing appropriate IC package types based on client specifications.
• Performing electrical analysis to identify limitations and potential issues in design.
• Optimising performance of IC packages by analysing routing and noise.
• Reviewing designs for manufacturability and cost optimisation.

Connaissances

IC package design

Signal integrity (SI) analysis

Power integrity (PI) analysis

Cadence layout tools

Ansys simulation tools

2.5D/3D packaging technologies

Communication skills

Formation

MSc in Electronics Engineering

Description du poste

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life‑saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

YOUR ROLE

As a Packaging Engineer, you will be responsible for designing and optimising IC packages for semiconductor applications, working closely with customers and suppliers to deliver high‑performance solutions. In this role you will play a key role in:

• Selecting and designing appropriate IC package types based on client specifications and IC requirements, including expertise in 2.5D/3D packaging and backend silicon layout
• Performing comprehensive signal integrity (SI) and power integrity (PI) simulations and electrical analysis to identify limitations and potential issues early in the design process
• Optimising electrical performance of IC packages by analysing routing, parasitic effects, noise, and electromagnetic compatibility (EMC), proposing design enhancements where needed
• Reviewing designs for manufacturability and cost optimisation, ensuring compatibility with manufacturing processes, assembly requirements, and material availability
• Producing detailed technical reports summarising analysis, simulations, design modifications, and optimisation recommendations, clearly communicating findings to customers and suppliers

YOUR PROFILE

• An MSc in Electronics Engineering or equivalent, combined with a minimum of 5 years of experience in IC package design and SI/PI analysis
• Hands‑on experience with Cadence layout tools for package and backend silicon design, including place & route
• Proficiency in Ansys simulation tools for electrical and electromagnetic performance analysis
• Strong knowledge of 2.5D/3D packaging technologies and an understanding of the full IC package design lifecycle, from concept through to manufacturing
• Excellent communication skills in English (written and spoken)