Software Engineering - D-Matrix Australia Pty Ltd

D-Matrix Australia Pty Ltd; Sydney; On-site; AUD 120,000 - 190,000; Full time

Job summary

d-Matrix Australia Pty Ltd is seeking a Senior Staff Runtime Engineer to lead the architecture, development and validation of firmware and software running on the SoC's multi-core processors and embedded subsystems.

You will collaborate with hardware teams across AU and US, bring software up on FPGA platforms, and drive performance, memory utilisation and power efficiency while meeting delivery milestones.

Qualifications

• Bachelor or Master of Science in Computer Science or Computer Engineering.
• Minimum 5 years of embedded software experience.
• Experience with multi-threaded C on multi-core CPUs running an RTOS in AMP and SMP configurations.
• Ability to interpret HW-centric data sheets and register definitions to determine how to best program the architecture.
• Experience with FPGA-based development and system emulators is an advantage.
• Knowledge of bootloaders and Linux device drivers is an advantage.

Responsibilities

• Design and develop runtime firmware for the SoC's multi-core processors and embedded subsystems.
• Architect, document and implement runtime firmware to maximise hardware utilisation.
• Bring software up on FPGA platforms and debug via JTAG-connected IDE.
• Collaborate with HW, SW and QA teams across AU/US/IND regions to meet milestones.
• Port software to emulation and big‑iron environments and validate performance.

Skills

Multi-threaded C programming

RTOS experience (AMP/SMP)

Many-core synchronization

JTAG debugging

Linux device drivers

SystemC modelling

FPGA-based development

Git/Jira/Jenkins/Kanban

Autonomy & milestone delivery

Education

Bachelor or Master of Science in Computer Science or Computer Engineering

Tools

Zephyr OS

PIC programming

System emulators (FPGA/SystemC)

Job description

Senior Staff Runtime Engineer

North Ryde, Full Time, IT Jobs

Vacancy Listing Dates 8/09/2026 to 6/10/2026
Please Quote Reference Number 18457

• Skilled Senior Staff Runtime Engineer required
• Full time opportunity
• Join the team at d-Matrix Australia Pty Ltd

What you will do:

d-Matrix is developing an AI inference processor for accelerating the inference of NLP, vision, and recommendation workloads in a data center environment. The architecture uses an in-memory compute processor subsystem, with a mix of fixed-point and floating-point data types in both dense and sparse matrix processing modes. During the seed round, the company has developed a CMOS test chip and validated the architecture using real inference workloads compiled from PyTorch.

The position is a Senior Staff Runtime Engineer to work on the architecture, development and validation of the functionality and efficiency of firmware/software that is executed on the system-on-chip's multiple processors, low-level drivers and system programs that host this system-on-chip.

In this role, you will be largely responsible for all aspects of runtime performance of the silicon product. You will architect, document, and develop the runtime firmware that executes in the various on-chip multi-core CPU subsystems. This firmware will be controlling all aspects of the AI subsystems in the chip and will be architected to maximise the utilisation of the hardware. Measures of success will be overall AI hardware utilisation, minimising communication bottlenecks, and maximising on-chip memory utilisation.

You will bring the software up on FPGA platforms (that contain images of the embedded CPU subsystems) and debug it using JTAG-connected IDE. You will develop a firmware solution that can be developed and tested ahead of the availability of the AI subsystem hardware.

You will be responsible for determining the delivery schedule and ensuring the software meets d-Matrix coding and methodology guidelines. You will collaborate with the hardware teams (to interpret the hardware specifications and suggest changes that improve utilization and throughput and/or reduce power). You will collaborate with other members of the SW team (located in AU and the US) and the SW quality & test team (US and India), as well as the HW verification team (to assist with SoC-level DV simulations and emulation).

You will be developing and debugging code on the FPGA-based systems containing CPU subsystems and SystemC models of the AI subsystems and SoC You will also be involved in porting the software to a 'big iron' emulation system (e.g., Veloce, Palladium) containing the final RTL.

You will also be closely involved in the bringing up of the software on the AI subsystem hardware and validating silicon and software performance.

What you will bring

• A Bachelor or Master of Science degree in computer science, computer engineering, or similar
• A minimum of 5 years of industry experience in embedded software development
• Experience with multi-threaded C programming on multi-core CPUs running an RTOS in both AMP and SMP configurations
• Understanding of methods used to synchronize many-core and many-CPU architectures
• Managing static resources without an MMU
• Zephyr OS experience is an advantage
• Experience with PIC programming and developing interrupt service routines
• Knowledge of bootloaders and Linux device drivers is an advantage
• Ability to interpret HW-centric data sheets and register definitions to determine how to best program the architecture
• Ability to work with HW design teams at both the early definition phase and during development
• Experience with FPGA-based development and system emulators is an advantage
• Ability to work with SW architecture teams and propose considered feedback on SW architecture
• Knowledge of assembly language programming of pipelined RISC architecture processors
• Runtime FW debugging on target hardware using IDE via JTAG
• Experience with current SW development methodologies, including Git, Kanban, sprints, Jenkins, and Jira (or similar)
• Experience collaborating in SW development projects that span multiple time zones and geographical regions
• Ability to work autonomously without day-to-day supervision, yet capable of delivering on agreed milestones in the development schedule (tracked weekly).
• Skills that include unit-level testing, documentation, and interfacing with QA & test teams
• Skills in mathematical quantization, floating-point arithmetic, block floating-point, sparse matrix processing, and linear algebra is an advantage