Senior Digital Engineer

Fi NOW; Sydney; Hybrid; AUD 180,000 - 240,000; Full time

Benefits offered by this job

Competitive salary

Excellent stock option package

Performance bonus opportunity

Relocation and visa support

Work from home policy

Job summary

Morse Micro, Australia’s largest fabless semiconductor company, is hiring a Senior Digital Engineer to deliver SystemVerilog and Chisel RTL across chip and subsystem levels. You will own microarchitecture, drive verification strategy, and translate market needs into technical specs for low-power IoT Wi‑Fi HaLow chips.

Join a VC-backed high-growth team and mentor peers while collaborating with firmware and analog teams to hit major milestones. Relocation and visa support available.

Qualifications

• Degree in Electrical/Electronics/CS with advanced studies preferred.
• 5+ years as a Senior Digital Engineer developing complex digital blocks or SoCs.
• Strong RTL design fundamentals, synthesis, and ECO implementation/debug.
• Proven Verilog/SystemVerilog expertise and digital verification experience.

Responsibilities

• Deliver SystemVerilog and Chisel RTL across chip, subsystem, and block levels.
• Own microarchitecture and design specs for digital logic.
• Direct verification strategy and test plan closure (RTL sims, GLS, X-prop, CDC/RDC, lint).
• Translate market direction into technical specs for features/performance.
• Enhance digital design and verification infrastructure and collaborate with firmware/PHY teams.
• Architect clocking, resets, and power domains; manage UPF/CPF power intent.
• Apply low-power techniques for IoT battery and energy-harvesting apps.
• Mentor junior engineers and drive design quality via reviews.

Skills

SystemVerilog

Chisel RTL

microarchitecture

digital verification

Python scripting

C programming

UPF/CPF power intent

low-power design

RTL design methodologies

team mentorship

Education

BSc/MSc/PhD in Electrical/Electronics/CS

Tools

Verilog/SystemVerilog

GLS/FPGA emulation

EDA tooling

Job description

Morse Micro is at the forefront of next-generation Wi-Fi technology, delivering breakthrough solutions that redefine wireless connectivity. Our innovative products are designed to meet the demands of the rapidly evolving market, providing superior performance and reliability.

Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things (IoT)? Keen to make a real difference in a VC-backed high-growth company while working in a dynamic & fun environment? Then join Morse Micro, Australia’s largest fabless semiconductor company!

We welcome applications from overseas candidates, with relocation and visa support available for the successful applicant.

Your responsibilities would include:

• Deliver SystemVerilog and Chisel RTL across chip, subsystem, and block levels, meeting PPA targets.
• Own microarchitecture and design specifications for chip-, subsystem-, and block-level digital logic.
• Drive verification strategy and test plan closure (RTL sims, GLS, X-prop, CDC/RDC, lint, FPGA emulation) through our phase-gate methodology.
• Derive product, subsystem, and block-level feature and performance requirements by studying competitor parts, tracking state of the art in low-power wireless/IoT SoCs, and translating market direction into technical specifications.
• Enhance and maintain our digital design and verification infrastructure.
• Architect clocking, reset, and power domains; author and close UPF/CPF power intent through to GLS and PA simulation.
• Apply low-power techniques (clock gating, power gating, retention, isolation) appropriate to battery- and energy-harvesting IoT applications.
• Integrate mixed-signal IP (ADPLL, PHY, pads, analog macros) and own the digital/analog interface contract.
• Partner with firmware and PHY/MAC teams on register interfaces, programming models, interrupts, and boot sequences to enable efficient HW/SW co-design.
• Take on chip-lead duties: drive system verification, synthesis QoR, P&R support, gate-level netlist and power-aware sims, ECO and LEC closure, and tapeout checklist completion.
• Coordinate across analog, layout, PnR, DFT, and SW teams to hit major project milestones.
• Use AI coding assistants and agents fluently across RTL, verification, scripting, and documentation tasks, with sound judgement on where they accelerate work and where they need close review.
• Identify opportunities to apply AI to our design and verification flows — spec analysis, test generation, debug, code review, infrastructure automation — and drive their adoption across the team.
• Deliver large, complex projects on schedule with multiple concurrent spins.
• Mentor junior team members and uphold design quality through reviews, coding standards, and methodology improvements.

Essential skills (you must have):

• Bsc/MSc/Phd in Electrical / Electronics / Communication Engineering or Computer Science
• 5+ years experience as a Senior Digital Engineer
• Proven experience in the development of complex digital blocks, subsystems, or SoC architectures
• Strong understanding of digital design fundamentals, RTL design methodologies, synthesis flows, and ECO implementation/debug
• Solid expertise in Verilog/SystemVerilog, digital verification methodologies, C programming, and CDC/RDC analysis
• Proficiency in scripting and automation using Python, Tcl, Shell, Makefiles, or similar languages/tools
• Experience with design automation and infrastructure development is highly desirable.
• Knowledge of low-power design techniques, including clock gating, power domains, power gating, retention, and isolation, is a plus
• Familiarity with embedded systems, bus or processor architectures is an advantage
• Excellent verbal and written communication skills
• Proven to work constructively within your team and among other groups
• Strong analytical and problem-solving skills
• A determination to deliver even when subject to time pressures
• A hands-on, practical attitude

What we offer:

• Competitive salary + excellent stock option package
• Performance Bonus opportunity
• Income protection Insurance
• Healthy work environment with sit/stand desks and large screens
• Lots of snacks & drinks, including barista coffee, Friday team lunches & some of the world’s best beers
• Work from home policy
• Community & social groups and much more
• Join a high performing, inclusive company where you can make a real impact

Who we are:

Morse Micro is Australia’s largest semiconductor company building Wi-Fi HaLow (802.11ah) chips for the Internet of Things (IoT). We are a team of wireless experts that love to work hard, innovate & invent. Together, we are building the world’s lowest power Wi-Fi technology that will enable billions of IoT devices to connect securely to the internet. We are a global team with offices in Sydney, Picton & Melbourne (Australia), Irvine & San Jose (USA), Bangalore (India), Cambridge (UK), Hangzhou & Shenzen (China), Taipei (Taiwan) and Tokyo (Japan).