Senior Engineer Mixed-Signal Verification (f/m/div)

Infineon Technologies; Villach; Vor Ort; EUR 60 000 - 80 000; Vollzeit

Zusammenfassung

A technology company in Austria is seeking a Verification Engineer for Analog/Mixed-Signal Products. You will be responsible for conducting top-level verification of mixed-signal designs and creating comprehensive verification tests. The ideal candidate has a degree in electrical engineering and expertise in programming languages like SystemVerilog, Perl, and Python. This role offers a competitive salary and the possibility of negotiation based on experience. Apply now!

Qualifikationen

• Conduct top-level verification of complex mixed-signal designs to ensure functionality and reliability.
• Create comprehensive verification plans and develop tests.
• Collaborate with cross-functional teams to track and report on test implementation and stimuli development.
• Deliver state-of-the-art documentation for all verification deliverables.
• Drive innovation by contributing to projects with focus on automation.
• Fluency in English is required, German is a plus.

Aufgaben

• Perform top-level verification of mixed-signal IP modules.
• Ensure alignment with verification plans across teams.

Kenntnisse

Programming in SystemVerilog

Perl

Python

MATLAB

Experience with simulators like XA, XA/VCS, Spectre, AMS-Designer

Knowledge of analog and digital design principles

Strong communication skills

Fluency in English

Ausbildung

Degree in electrical engineering or a related field

Tools

UNIX environment

MS Office tools

JAMA

JIRA

Datamanagement (GIT/Perforce)

Jobbeschreibung

You are looking for a new challenge to bring in your broad knowledge of AMS verification? Then this is the right job for you: as our new Verification Engineer for Analog/Mixed-Signal Products you will perform top-level verification of mixed-signal IP modules. Sounds interesting? Then apply now!

In your new Mixed-Signal Verification role you will:

• Conduct top-level verification of complex mixed-signal designs to ensure functionality and reliability
• Create comprehensive verification plans and develop tests
• Collaborate with cross-functional teams to track and report on test implementation and stimuli development, ensuring alignment with verification plans
• Deliver state-of-the-art documentation for all verification deliverables
• Drive innovation by contributing to projects, e.g. AI and machine learning methods in verification, UVM methods in mixed signal verification, all with a focus on automation and enhancement of the mixed-signal verification workflow

You are best equipped for this task if you have:

• A degree in electrical engineering or a related field
• Proficiency in programming languages and tools, such as SystemVerilog, Perl, Python, MATLAB, paired with strong experience in simulators like XA, XA/VCS, Spectre, or AMS-Designer
• Working experience with UNIX environment
• Knowledge of MS Office tools and familiarity with tools like JAMA, JIRA, Datamanagement (GIT/Perforce)
• Valuable know-how in analog and digital design principles, as well as SPICE and SystemVerilog
• Strong communication skills complemented by a team-focused and proactive working style
• Fluency in English (German language skills are an advantage)

A valid work permit for Austria (RWR+ Card) or EU citizenship is a prerequisite for this position. This position is subject to the collective agreement for workers and employees of EEI with a minimum salary of € 4.341,85 (https://www.feei.at/wp-content/uploads/2023/05/minimum-salaries-white-collar-workers-2024.pdf). The monthly salary is paid 14 times p.a. A higher payment is negotiable depending on your expertise and skills.

Contact: Mag. Carmen Schmidt, LinkedIn

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