Experienced Cellular IP Design Engineer (m/f/d)

Apple; Linz; Vor Ort; EUR 73.422 - 89.738; Vollzeit

Zusammenfassung

Apple is seeking an experienced IP Design Engineer for its Cellular SoC IP team located in Linz. In this role, you will be responsible for developing and integrating customized hardware IPs for digital signal processing. Key responsibilities include collaborating with various engineering teams, optimizing power and performance, and addressing technical challenges using tools like Verilog and System Verilog. A Bachelor's or Master's degree in Electrical Engineering is required, and the minimum salary for this full-time role is €81,580 gross per year.

Qualifikationen

• Experience designing low-power hardware for digital signal processing.
• Advanced skills in ASIC or FPGA designs.
• Proficient in analyzing RTL/Netlist designs.

Aufgaben

• Developing, integrating & verifying IP components for cellular transceivers.
• Collaborating with cross-disciplinary teams throughout the project lifecycle.
• Responsible for timing closure and power optimizations.

Kenntnisse

Low-power hardware design

Digital signal processing

Verilog/System Verilog

Debugging skills

Scripting languages (TCL, Python)

Interpersonal skills

Problem-solving

Ausbildung

Bachelor's or Master's in Electrical Engineering or equivalent

Ph.D. in relevant fields (optional)

Tools

Linux

Revision control systems (e.g., Perforce)

Jobbeschreibung

Summary

In this role, you will be a key part of the Cellular SoC IP team in Munich or Linz. As an IP Design engineer, you are responsible for developing highly customized hardware IPs for digital signal processing and integrating IPs into SoCs. You will work closely with SoC architects, System engineers, Design verification, Silicon validation teams, STA/DFT/Power specialists, and Physical designers to develop IPs & SoCs that meet Apple devices’ power, performance, and area goals.

Description

As a Cellular design engineer, you will be developing, integrating & verifying IP sub-components for a cellular transceiver System on a Chip. You would be responsible for defining and driving the implementation, timing closure, and power optimizations in close collaboration with a multi-disciplinary group from system, digital, analog & firmware design, to design verification, and physical design teams, which will support your daily work. Your work will not be limited to design. It will cover end‑to‑end responsibility across the project lifecycle for the IPs developed from concept to design, verification, integration, silicon validation, and finally, in‑field operation.

Minimum Qualifications

• Experienced with crafting low‑power customized hardware for digital signal processing. Understanding of signal processing principles. Abstract modeling skills for synthesis and simulation using modern modeling language. (Verilog / System Verilog).
• Advanced hands‑on experience in multiple sophisticated ASIC or FPGA designs, spanning from concept to productization.
• Good hands‑on experience with digital logic design and quality checks, such as Lint and CDC/RDC.
• Proficient in using (System)Verilog, the ability to analyze RTL/Netlist designs, and outstanding debugging skills to solve technical challenges.
• Familiar with day‑to‑day usage of scripting languages (e.g., TCL, Python, Perl, shell), Linux, and revision control systems (e.g., Perforce), database management, and releases.
• Passion for owning/driving design topics using well‑defined metrics, a strong initiative, and ownership of responsibilities, productive, and able to meet daring deadlines.
• Advanced interpersonal skills and the ability to communicate abstract concepts to different stakeholders. Excellent problem‑solving skills and the ability to find effective technical solutions between partners in RTL design, Firmware, System Engineering, Power, and Physical Design teams.
• English language proficiency is a requirement for this position.

Preferred Qualifications

• Experience with on‑chip communication buses & fabrics like AMBA/Wishbone and processor sub‑systems would be a plus.
• Experience with SystemC/C++ hardware design modeling, high‑level synthesis, and logical synthesis would be desirable.
• Experience applying Machine Learning or AI techniques to optimize digital hardware design processes and workflows (e.g., RTL generation, power/timing optimization, design space exploration, or design flow automation).
• A bachelor's or master’s, or Ph.D. in electrical engineering, Communication Engineering, Computer Science/ Software Engineering, or equivalent, paired with extensive years of industry work experience.
• The minimum salary pursuant to the applicable collective bargaining agreement amounts to €81,580 gross per year for full‑time employment. Actual salaries are oriented at current market salaries and take your qualifications and experience into account.
• Apple is an equal‑opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other legally protected characteristics. Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities.
• At Apple, we believe in creating products that serve everyone. We draw on all perspectives in our culture, benefits and digital tools to ensure a welcoming environment where all feel they belong.
• At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools.

Additional Information

Learn about accessibility in Apple’s workplace.
Role Number: 200662856‑4265